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| author | George Shen <george.shen@amd.com> | 2024-06-17 16:32:15 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2024-07-01 16:06:53 -0400 |
| commit | 95134e5852978a92d2290a3b1ee93189e75507ac (patch) | |
| tree | 9b5df7fbb7101ba1c901c25de1cc73d24c78c7c6 /drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c | |
| parent | drm/amd/display: Revert Add workaround to restrict max frac urgent for DPM0 (diff) | |
| download | linux-95134e5852978a92d2290a3b1ee93189e75507ac.tar.gz linux-95134e5852978a92d2290a3b1ee93189e75507ac.zip | |
drm/amd/display: Add ASIC cap to limit DCC surface width
[Why]
Certain configurations of DCN401 require ODM4:1 to support DCC for 10K
surfaces. DCC should be conservatively disabled in those cases.
The issue is that current logic limits 10K surface DCC for all
configurations of DCN401.
[How]
Add DC ASIC cap to indicate max surface width that can support DCC.
Disable DCC if this ASIC cap is non-zero and surface width exceeds it.
Reviewed-by: Jun Lei <jun.lei@amd.com>
Signed-off-by: Jerry Zuo <jerry.zuo@amd.com>
Signed-off-by: George Shen <george.shen@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c')
0 files changed, 0 insertions, 0 deletions