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authorAurabindo Pillai <aurabindo.pillai@amd.com>2024-03-20 13:56:16 -0400
committerAlex Deucher <alexander.deucher@amd.com>2024-04-26 17:23:34 -0400
commit00c391102abc13763e2bfc90e05503109b19f074 (patch)
tree105c9c3403e562878cb5c3ea7f2fbc587e7ce48d /drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
parentdrm/amd/display: Add some DCN401 reg name to macro definitions (diff)
downloadlinux-00c391102abc13763e2bfc90e05503109b19f074.tar.gz
linux-00c391102abc13763e2bfc90e05503109b19f074.zip
drm/amd/display: Add misc DC changes for DCN401
Add miscellaneous changes to enable DCN401 init Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h')
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h8
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
index f600b7431e23..0721ae895ae9 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
@@ -307,6 +307,14 @@ bool dcn31_clk_src_construct(
const struct dce110_clk_src_shift *cs_shift,
const struct dce110_clk_src_mask *cs_mask);
+bool dcn401_clk_src_construct(
+ struct dce110_clk_src *clk_src,
+ struct dc_context *ctx,
+ struct dc_bios *bios,
+ enum clock_source_id id,
+ const struct dce110_clk_src_regs *regs,
+ const struct dce110_clk_src_shift *cs_shift,
+ const struct dce110_clk_src_mask *cs_mask);
/* this table is use to find *1.001 and /1.001 pixel rates from non-precise pixel rate */
struct pixel_rate_range_table_entry {
unsigned int range_min_khz;