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authorAlex Deucher <alexander.deucher@amd.com>2018-08-14 14:53:52 -0500
committerAlex Deucher <alexander.deucher@amd.com>2018-08-27 11:11:15 -0500
commit11c3ee48bd7c232c0a750b4dde8ee48f315dcdf3 (patch)
tree49355f0f09b5f06fa3b4bc00c8f0c3bd6bb3bfa7 /drivers/gpu/drm/amd/display/dc/dce
parentdrm/amdgpu: Don't use kiq in gpu reset (diff)
downloadlinux-11c3ee48bd7c232c0a750b4dde8ee48f315dcdf3.tar.gz
linux-11c3ee48bd7c232c0a750b4dde8ee48f315dcdf3.zip
drm/amdgpu/display: add support for LVDS (v5)
This adds support for LVDS displays. v2: add support for spread spectrum, sink detect v3: clean up enable_lvds_output v4: fix up link_detect v5: remove assert on 888 format Bug: https://bugs.freedesktop.org/show_bug.cgi?id=105880 Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dce')
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c10
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h2
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c34
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h6
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c24
5 files changed, 76 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
index ca137757a69e..1f23224d495a 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
@@ -75,6 +75,11 @@ static const struct spread_spectrum_data *get_ss_data_entry(
entrys_num = clk_src->hdmi_ss_params_cnt;
break;
+ case SIGNAL_TYPE_LVDS:
+ ss_parm = clk_src->lvds_ss_params;
+ entrys_num = clk_src->lvds_ss_params_cnt;
+ break;
+
case SIGNAL_TYPE_DISPLAY_PORT:
case SIGNAL_TYPE_DISPLAY_PORT_MST:
case SIGNAL_TYPE_EDP:
@@ -1184,6 +1189,11 @@ static void ss_info_from_atombios_create(
AS_SIGNAL_TYPE_DVI,
&clk_src->dvi_ss_params,
&clk_src->dvi_ss_params_cnt);
+ get_ss_info_from_atombios(
+ clk_src,
+ AS_SIGNAL_TYPE_LVDS,
+ &clk_src->lvds_ss_params,
+ &clk_src->lvds_ss_params_cnt);
}
static bool calc_pll_max_vco_construct(
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
index c45e2f76189e..cdeb96a268fb 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
@@ -125,6 +125,8 @@ struct dce110_clk_src {
uint32_t hdmi_ss_params_cnt;
struct spread_spectrum_data *dvi_ss_params;
uint32_t dvi_ss_params_cnt;
+ struct spread_spectrum_data *lvds_ss_params;
+ uint32_t lvds_ss_params_cnt;
uint32_t ext_clk_khz;
uint32_t ref_freq_khz;
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
index eff7d22d78fb..4942590e8b9c 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
@@ -102,6 +102,7 @@ static const struct link_encoder_funcs dce110_lnk_enc_funcs = {
.enable_tmds_output = dce110_link_encoder_enable_tmds_output,
.enable_dp_output = dce110_link_encoder_enable_dp_output,
.enable_dp_mst_output = dce110_link_encoder_enable_dp_mst_output,
+ .enable_lvds_output = dce110_link_encoder_enable_lvds_output,
.disable_output = dce110_link_encoder_disable_output,
.dp_set_lane_settings = dce110_link_encoder_dp_set_lane_settings,
.dp_set_phy_pattern = dce110_link_encoder_dp_set_phy_pattern,
@@ -814,6 +815,7 @@ bool dce110_link_encoder_validate_output_with_stream(
enc110, &stream->timing);
break;
case SIGNAL_TYPE_EDP:
+ case SIGNAL_TYPE_LVDS:
is_valid =
(stream->timing.
pixel_encoding == PIXEL_ENCODING_RGB) ? true : false;
@@ -955,6 +957,38 @@ void dce110_link_encoder_enable_tmds_output(
}
}
+/* TODO: still need depth or just pass in adjusted pixel clock? */
+void dce110_link_encoder_enable_lvds_output(
+ struct link_encoder *enc,
+ enum clock_source_id clock_source,
+ uint32_t pixel_clock)
+{
+ struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
+ struct bp_transmitter_control cntl = { 0 };
+ enum bp_result result;
+
+ /* Enable the PHY */
+ cntl.connector_obj_id = enc110->base.connector;
+ cntl.action = TRANSMITTER_CONTROL_ENABLE;
+ cntl.engine_id = enc->preferred_engine;
+ cntl.transmitter = enc110->base.transmitter;
+ cntl.pll_id = clock_source;
+ cntl.signal = SIGNAL_TYPE_LVDS;
+ cntl.lanes_number = 4;
+
+ cntl.hpd_sel = enc110->base.hpd_source;
+
+ cntl.pixel_clock = pixel_clock;
+
+ result = link_transmitter_control(enc110, &cntl);
+
+ if (result != BP_RESULT_OK) {
+ DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
+ __func__);
+ BREAK_TO_DEBUGGER();
+ }
+}
+
/* enables DP PHY output */
void dce110_link_encoder_enable_dp_output(
struct link_encoder *enc,
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h
index 347069461a22..3c9368df4093 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h
@@ -225,6 +225,12 @@ void dce110_link_encoder_enable_dp_mst_output(
const struct dc_link_settings *link_settings,
enum clock_source_id clock_source);
+/* enables LVDS PHY output */
+void dce110_link_encoder_enable_lvds_output(
+ struct link_encoder *enc,
+ enum clock_source_id clock_source,
+ uint32_t pixel_clock);
+
/* disable PHY output */
void dce110_link_encoder_disable_output(
struct link_encoder *enc,
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
index 91642e684858..c47c81883d3c 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
@@ -674,6 +674,28 @@ static void dce110_stream_encoder_dvi_set_stream_attribute(
dce110_stream_encoder_set_stream_attribute_helper(enc110, crtc_timing);
}
+/* setup stream encoder in LVDS mode */
+static void dce110_stream_encoder_lvds_set_stream_attribute(
+ struct stream_encoder *enc,
+ struct dc_crtc_timing *crtc_timing)
+{
+ struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
+ struct bp_encoder_control cntl = {0};
+
+ cntl.action = ENCODER_CONTROL_SETUP;
+ cntl.engine_id = enc110->base.id;
+ cntl.signal = SIGNAL_TYPE_LVDS;
+ cntl.enable_dp_audio = false;
+ cntl.pixel_clock = crtc_timing->pix_clk_khz;
+ cntl.lanes_number = LANE_COUNT_FOUR;
+
+ if (enc110->base.bp->funcs->encoder_control(
+ enc110->base.bp, &cntl) != BP_RESULT_OK)
+ return;
+
+ ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB);
+}
+
static void dce110_stream_encoder_set_mst_bandwidth(
struct stream_encoder *enc,
struct fixed31_32 avg_time_slots_per_mtp)
@@ -1564,6 +1586,8 @@ static const struct stream_encoder_funcs dce110_str_enc_funcs = {
dce110_stream_encoder_hdmi_set_stream_attribute,
.dvi_set_stream_attribute =
dce110_stream_encoder_dvi_set_stream_attribute,
+ .lvds_set_stream_attribute =
+ dce110_stream_encoder_lvds_set_stream_attribute,
.set_mst_bandwidth =
dce110_stream_encoder_set_mst_bandwidth,
.update_hdmi_info_packets =