diff options
| author | Qingqing Zhuo <Qingqing.Zhuo@amd.com> | 2023-08-03 01:12:01 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2023-08-30 15:51:14 -0400 |
| commit | 33e36f8e503881ec4009b16278dc390c10a3d526 (patch) | |
| tree | 03e9aef54c899b25ad9a29d21b1896b8f4d41d52 /drivers/gpu/drm/amd/display | |
| parent | drm/amd/display: Update DCN314 for DCN35 support (diff) | |
| download | linux-33e36f8e503881ec4009b16278dc390c10a3d526.tar.gz linux-33e36f8e503881ec4009b16278dc390c10a3d526.zip | |
drm/amd/display: Update DCN32 for DCN35 support
[Why & How]
Update DCN32 files for DCN35 usage.
Signed-off-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display')
4 files changed, 0 insertions, 9 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.h index c8a3a6a96ff7..5198f2167c7c 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.h +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.h @@ -779,7 +779,6 @@ type MPCC_MCM_1DLUT_LUT_DATA;\ type MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK;\ type MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL;\ - type MPCC_MCM_1DLUT_LUT_READ_DBG;\ type MPCC_MCM_1DLUT_LUT_HOST_SEL;\ type MPCC_MCM_1DLUT_LUT_CONFIG_MODE;\ type MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B;\ diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mmhubbub.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mmhubbub.h index e460cf8d9041..ef15b4f1f6b9 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mmhubbub.h +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mmhubbub.h @@ -43,8 +43,6 @@ SRI2(MCIF_WB_BUF_4_STATUS2, MCIF_WB, inst),\ SRI2(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB, inst),\ SRI2(MCIF_WB_SCLK_CHANGE, MCIF_WB, inst),\ - SRI2(MCIF_WB_TEST_DEBUG_INDEX, MCIF_WB, inst),\ - SRI2(MCIF_WB_TEST_DEBUG_DATA, MCIF_WB, inst),\ SRI2(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB, inst),\ SRI2(MCIF_WB_BUF_1_ADDR_C, MCIF_WB, inst),\ SRI2(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB, inst),\ @@ -157,8 +155,6 @@ SF(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_CLIENT_ARBITRATION_SLICE, mask_sh),\ SF(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_TIME_PER_PIXEL, mask_sh),\ SF(MCIF_WB_SCLK_CHANGE, WM_CHANGE_ACK_FORCE_ON, mask_sh),\ - SF(MCIF_WB_TEST_DEBUG_INDEX, MCIF_WB_TEST_DEBUG_INDEX, mask_sh),\ - SF(MCIF_WB_TEST_DEBUG_DATA, MCIF_WB_TEST_DEBUG_DATA, mask_sh),\ SF(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB_BUF_1_ADDR_Y, mask_sh),\ SF(MCIF_WB_BUF_1_ADDR_C, MCIF_WB_BUF_1_ADDR_C, mask_sh),\ SF(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB_BUF_2_ADDR_Y, mask_sh),\ diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.h index 9ac584fa89ce..9622518826c9 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.h +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.h @@ -232,7 +232,6 @@ SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_SELECT_CURRENT, mask_sh),\ SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_WRITE_COLOR_MASK, mask_sh),\ SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_READ_COLOR_SEL, mask_sh),\ - SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_READ_DBG, mask_sh),\ SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_HOST_SEL, mask_sh),\ SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_CONFIG_MODE, mask_sh),\ SF(MPCC_OGAM0_MPCC_OGAM_LUT_DATA, MPCC_OGAM_LUT_DATA, mask_sh),\ @@ -276,7 +275,6 @@ SF(MPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA, MPCC_MCM_1DLUT_LUT_DATA, mask_sh),\ SF(MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL, MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK, mask_sh),\ SF(MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL, MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL, mask_sh),\ - SF(MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL, MPCC_MCM_1DLUT_LUT_READ_DBG, mask_sh),\ SF(MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL, MPCC_MCM_1DLUT_LUT_HOST_SEL, mask_sh),\ SF(MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL, MPCC_MCM_1DLUT_LUT_CONFIG_MODE, mask_sh),\ SF(MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B, MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B, mask_sh),\ diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h index 4caebcaca031..c76de61029e0 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h @@ -713,8 +713,6 @@ bool dcn32_subvp_vblank_admissable(struct dc *dc, struct dc_state *context, int SRI2_ARR(MCIF_WB_BUF_4_STATUS2, MCIF_WB, inst), \ SRI2_ARR(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB, inst), \ SRI2_ARR(MCIF_WB_SCLK_CHANGE, MCIF_WB, inst), \ - SRI2_ARR(MCIF_WB_TEST_DEBUG_INDEX, MCIF_WB, inst), \ - SRI2_ARR(MCIF_WB_TEST_DEBUG_DATA, MCIF_WB, inst), \ SRI2_ARR(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB, inst), \ SRI2_ARR(MCIF_WB_BUF_1_ADDR_C, MCIF_WB, inst), \ SRI2_ARR(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB, inst), \ |