diff options
| author | Ausef Yousof <Ausef.Yousof@amd.com> | 2025-05-29 18:22:21 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2025-06-18 12:19:17 -0400 |
| commit | f6d7238c924b63303a77a93d7fa9fd4f307d9bca (patch) | |
| tree | 593b6fa759b260f73c4f477e8d0a8e8a294daa25 /drivers/gpu/drm/amd/display | |
| parent | drm/amd/display: Add option to disable PHY SSC reduction on transmitter enable (diff) | |
| download | linux-f6d7238c924b63303a77a93d7fa9fd4f307d9bca.tar.gz linux-f6d7238c924b63303a77a93d7fa9fd4f307d9bca.zip | |
drm/amd/display: Adjust dto fix coverage
[WHY & HOW]
Unnecessary to affect legacy APU's dto src sel during dpms behaviour
Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Signed-off-by: Ausef Yousof <Ausef.Yousof@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c index a9a3001109c3..c717cc1eca6d 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c @@ -1186,7 +1186,7 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx) if (dccg) { dccg->funcs->disable_symclk32_se(dccg, dp_hpo_inst); dccg->funcs->set_dpstreamclk(dccg, REFCLK, tg->inst, dp_hpo_inst); - if (dc->ctx->dce_version == DCN_VERSION_3_15) { + if (!(dc->ctx->dce_version >= DCN_VERSION_3_5)) { if (dccg && dccg->funcs->set_dtbclk_dto) dccg->funcs->set_dtbclk_dto(dccg, &dto_params); } diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c index bc06b7b3d67d..6a00f0984ce1 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c @@ -2871,7 +2871,7 @@ void dcn20_reset_back_end_for_pipe( link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF; } if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx) && dccg - && dc->ctx->dce_version != DCN_VERSION_3_15) { + && dc->ctx->dce_version >= DCN_VERSION_3_5) { dto_params.otg_inst = pipe_ctx->stream_res.tg->inst; dto_params.timing = &pipe_ctx->stream->timing; if (dccg && dccg->funcs->set_dtbclk_dto) |