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| author | Alex Sierra <alex.sierra@amd.com> | 2023-11-20 11:31:32 -0600 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2023-11-29 16:48:59 -0500 |
| commit | 20b07b0cb3a0a2fb3a6daf00f645925be77ec80c (patch) | |
| tree | 7e4103975f6ff625d3fbf36d19f6b1b0ccbca60f /drivers/gpu/drm/amd/include | |
| parent | drm/amdgpu: Do not issue gpu reset from nbio v7_9 bif interrupt (diff) | |
| download | linux-20b07b0cb3a0a2fb3a6daf00f645925be77ec80c.tar.gz linux-20b07b0cb3a0a2fb3a6daf00f645925be77ec80c.zip | |
drm/amdgpu: Force order between a read and write to the same address
Setting register to force ordering to prevent read/write or write/read
hazards for un-cached modes.
Signed-off-by: Alex Sierra <alex.sierra@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/include')
| -rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h index c92c4b83253f..4bff1ef8a9a6 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h @@ -6369,6 +6369,8 @@ #define regTCP_INVALIDATE_BASE_IDX 1 #define regTCP_STATUS 0x19a1 #define regTCP_STATUS_BASE_IDX 1 +#define regTCP_CNTL 0x19a2 +#define regTCP_CNTL_BASE_IDX 1 #define regTCP_CNTL2 0x19a3 #define regTCP_CNTL2_BASE_IDX 1 #define regTCP_DEBUG_INDEX 0x19a5 |