diff options
| author | Yang Wang <kevinyang.wang@amd.com> | 2023-09-04 16:32:30 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2023-09-20 16:24:06 -0400 |
| commit | 25396684b57f7d16306ca149c545db60b2d08dda (patch) | |
| tree | ee1456a48e86e0a5a1182c989170483f205321d0 /drivers/gpu/drm/amd/include | |
| parent | drm/amd/pm: update smu_v13_0_6 ppsmc header (diff) | |
| download | linux-25396684b57f7d16306ca149c545db60b2d08dda.tar.gz linux-25396684b57f7d16306ca149c545db60b2d08dda.zip | |
drm/amd/pm: add smu_13_0_6 mca dump support
v1:
implement smu_v13_0_6 mca bank interface.
v2:
- remove unnecessary lock
- move MCMP1_* macros to mp_13_0_6_sh_mask.h file
Signed-off-by: Yang Wang <kevinyang.wang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/include')
| -rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_6_sh_mask.h | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_6_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_6_sh_mask.h index 780d9824d5ed..2684e396f548 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_6_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_6_sh_mask.h @@ -670,5 +670,33 @@ #define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x00000001L #define MP1_FIRMWARE_FLAGS__RESERVED_MASK 0xFFFFFFFEL +//MCMP1_IPIDT0 +#define MCMP1_IPIDT0__InstanceIdLo__SHIFT 0x0 +#define MCMP1_IPIDT0__HardwareID__SHIFT 0x20 +#define MCMP1_IPIDT0__InstanceIdHi__SHIFT 0x2c +#define MCMP1_IPIDT0__McaType__SHIFT 0x30 + +#define MCMP1_IPIDT0__InstanceIdLo_MASK 0x00000000FFFFFFFFL +#define MCMP1_IPIDT0__HardwareID_MASK 0x00000FFF00000000L +#define MCMP1_IPIDT0__InstanceIdHi_MASK 0x0000F00000000000L +#define MCMP1_IPIDT0__McaType_MASK 0xFFFF000000000000L + +//MCMP1_STATUST0 +#define MCMP1_STATUST0__ErrorCode__SHIFT 0x0 +#define MCMP1_STATUST0__ErrorCodeExt__SHIFT 0x10 +#define MCMP1_STATUST0__PCC__SHIFT 0x39 +#define MCMP1_STATUST0__UC__SHIFT 0x3d +#define MCMP1_STATUST0__Val__SHIFT 0x3f + +#define MCMP1_STATUST0__ErrorCode_MASK 0x000000000000FFFFL +#define MCMP1_STATUST0__ErrorCodeExt_MASK 0x00000000003F0000L +#define MCMP1_STATUST0__PCC_MASK 0x0200000000000000L +#define MCMP1_STATUST0__UC_MASK 0x2000000000000000L +#define MCMP1_STATUST0__Val_MASK 0x8000000000000000L + +//MCMP1_MISC0T0 +#define MCMP1_MISC0T0__ErrCnt__SHIFT 0x20 + +#define MCMP1_MISC0T0__ErrCnt_MASK 0x00000FFF00000000L #endif |