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| author | Lijo Lazar <lijo.lazar@amd.com> | 2025-01-10 12:58:49 +0530 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2025-02-12 21:02:55 -0500 |
| commit | 822b13d19fac05b8299f9e3636dbcce246867d2f (patch) | |
| tree | a452fc0179824c8af28a9ff3b74ba1769bf1c2a0 /drivers/gpu/drm/amd/include | |
| parent | drm/amdgpu: add support for PSP IP version 14.0.5 (diff) | |
| download | linux-822b13d19fac05b8299f9e3636dbcce246867d2f.tar.gz linux-822b13d19fac05b8299f9e3636dbcce246867d2f.zip | |
drm/amdgpu: Add VCN v4.0.3 RRMT register offset
Add RRMT control register offset for VCN v4.0.3
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/include')
| -rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_offset.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_offset.h index e9742d10de1c..a0e27aefb56d 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_offset.h @@ -779,7 +779,8 @@ #define regUVD_LMI_MIF_REF_LUMA_64BIT_BAR_HIGH_BASE_IDX 1 #define regVCN_RAS_CNTL 0x02df #define regVCN_RAS_CNTL_BASE_IDX 1 - +#define regVCN_RRMT_CNTL 0x0940 +#define regVCN_RRMT_CNTL_BASE_IDX 1 // addressBlock: aid_uvd0_uvd_jpeg0_jpegnpdec // base address: 0x20f00 |