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| author | Mika Kuoppala <mika.kuoppala@linux.intel.com> | 2019-04-05 21:46:56 +0100 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2019-04-11 09:20:04 +0100 |
| commit | 7d4c75d9097a0031b0aabf0bbc127ae7dcf93de3 (patch) | |
| tree | 061b87d6eba817b06c370ceb18e3f2537ac7f4ce /drivers/gpu/drm/i915/intel_dp_mst.c | |
| parent | drm/i915: Use Engine1 instance for gen11 pm interrupts (diff) | |
| download | linux-7d4c75d9097a0031b0aabf0bbc127ae7dcf93de3.tar.gz linux-7d4c75d9097a0031b0aabf0bbc127ae7dcf93de3.zip | |
drm/i915: Prepare for larger CSB status FIFO size
Make csb entry count variable in preparation for larger
CSB status FIFO size found on gen11+ hardware.
v2: adapt to hwsp access only (Chris)
non continuous mmio (Daniele)
v3: entries (Chris), fix macro for checkpatch
v4: num_entries (Chris)
v5: consistency on num_entries
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190405204657.12887-1-chris@chris-wilson.co.uk
Diffstat (limited to 'drivers/gpu/drm/i915/intel_dp_mst.c')
0 files changed, 0 insertions, 0 deletions