diff options
| author | Tom St Denis <tom.stdenis@amd.com> | 2025-03-06 12:31:56 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2025-03-07 15:33:48 -0500 |
| commit | 0d1a686b542aaabfcfd254bc7711624d4ec20df0 (patch) | |
| tree | 97213f5e9f8296b4ecca827d96a426cf5a73280c /drivers/gpu | |
| parent | drm/amdkfd: clear F8_MODE for gfx950 (diff) | |
| download | linux-0d1a686b542aaabfcfd254bc7711624d4ec20df0.tar.gz linux-0d1a686b542aaabfcfd254bc7711624d4ec20df0.zip | |
drm/amd/amdgpu: Add missing GC 11.5.0 register
Adds register needed for debugging purposes.
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_offset.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_offset.h index abdb8728156e..d6c02cf815be 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_offset.h @@ -9478,6 +9478,8 @@ #define regRLC_GFX_IMU_CMD_BASE_IDX 1 #define regGFX_IMU_RLC_STATUS 0x4054 #define regGFX_IMU_RLC_STATUS_BASE_IDX 1 +#define regGFX_IMU_STATUS 0x4055 +#define regGFX_IMU_STATUS_BASE_IDX 1 #define regGFX_IMU_SOC_DATA 0x4059 #define regGFX_IMU_SOC_DATA_BASE_IDX 1 #define regGFX_IMU_SOC_ADDR 0x405a |