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| author | Imre Deak <imre.deak@intel.com> | 2025-08-05 10:36:59 +0300 |
|---|---|---|
| committer | Imre Deak <imre.deak@intel.com> | 2025-08-13 15:03:29 +0300 |
| commit | 24d1cdacac11ddc3388714c5f82d31a480659ac7 (patch) | |
| tree | b2059fe12100a446e7c1fb8aa071ca1b673d8cc6 /drivers/gpu | |
| parent | dmc/i915/tc: Report pin assignment NONE in TBT-alt mode (diff) | |
| download | linux-24d1cdacac11ddc3388714c5f82d31a480659ac7.tar.gz linux-24d1cdacac11ddc3388714c5f82d31a480659ac7.zip | |
drm/i915/tc: Cache the pin assignment value
Cache the pin assignment value. This is more consistent with the way the
max lane count value is tracked and a bit more efficient than reading
out the same value from HW each time it's queried.
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Link: https://lore.kernel.org/r/20250805073700.642107-19-imre.deak@intel.com
Signed-off-by: Imre Deak <imre.deak@intel.com>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_tc.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c index 3e53332f804f..706f60a7d291 100644 --- a/drivers/gpu/drm/i915/display/intel_tc.c +++ b/drivers/gpu/drm/i915/display/intel_tc.c @@ -61,6 +61,7 @@ struct intel_tc_port { enum tc_port_mode mode; enum tc_port_mode init_mode; enum phy_fia phy_fia; + enum intel_tc_pin_assignment pin_assignment; u8 phy_fia_idx; u8 max_lane_count; }; @@ -382,6 +383,7 @@ static int get_max_lane_count(struct intel_tc_port *tc) static void read_pin_configuration(struct intel_tc_port *tc) { + tc->pin_assignment = get_pin_assignment(tc); tc->max_lane_count = get_max_lane_count(tc); } @@ -403,7 +405,7 @@ intel_tc_port_get_pin_assignment(struct intel_digital_port *dig_port) if (!intel_encoder_is_tc(&dig_port->base)) return INTEL_TC_PIN_ASSIGNMENT_NONE; - return get_pin_assignment(tc); + return tc->pin_assignment; } void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port, |