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| author | Mika Kahola <mika.kahola@intel.com> | 2025-11-17 12:45:56 +0200 |
|---|---|---|
| committer | Mika Kahola <mika.kahola@intel.com> | 2025-11-19 13:32:26 +0200 |
| commit | 57cf9d5e45a88a4d3543dfd32c78f9bedca1b110 (patch) | |
| tree | 54067273c8fef7cd50105d0a6915a00c510f0740 /drivers/gpu | |
| parent | 685f36534968467a37ee7319673633b82dcebe09 (diff) | |
| download | linux-57cf9d5e45a88a4d3543dfd32c78f9bedca1b110.tar.gz linux-57cf9d5e45a88a4d3543dfd32c78f9bedca1b110.zip | |
drm/i915/cx0: Add MTL+ .get_freq hook
Add .get_freq hook to support dpll framework for MTL+
platforms.
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://lore.kernel.org/r/20251117104602.2363671-27-mika.kahola@intel.com
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index beaf270294ca..85b3fee2d9b6 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -4379,8 +4379,21 @@ static bool mtl_pll_get_hw_state(struct intel_display *display, return intel_cx0pll_readout_hw_state(encoder, &dpll_hw_state->cx0pll); } +static int mtl_pll_get_freq(struct intel_display *display, + const struct intel_dpll *pll, + const struct intel_dpll_hw_state *dpll_hw_state) +{ + struct intel_encoder *encoder = get_intel_encoder(display, pll); + + if (drm_WARN_ON(display->drm, !encoder)) + return -EINVAL; + + return intel_cx0pll_calc_port_clock(encoder, &dpll_hw_state->cx0pll); +} + static const struct intel_dpll_funcs mtl_pll_funcs = { .get_hw_state = mtl_pll_get_hw_state, + .get_freq = mtl_pll_get_freq, }; static const struct dpll_info mtl_plls[] = { |