diff options
| author | Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> | 2025-06-26 11:02:39 +0200 |
|---|---|---|
| committer | Rob Clark <robin.clark@oss.qualcomm.com> | 2025-07-04 17:48:40 -0700 |
| commit | 709dd2ff2357734f5a0b2ef68e1f7c4256543a70 (patch) | |
| tree | 603f26783fabe8ee1784019562eb0427426f841b /drivers/gpu | |
| parent | soc: qcom: ubwc: Fix SM6125's ubwc_swizzle value (diff) | |
| download | linux-709dd2ff2357734f5a0b2ef68e1f7c4256543a70.tar.gz linux-709dd2ff2357734f5a0b2ef68e1f7c4256543a70.zip | |
soc: qcom: ubwc: Add #defines for UBWC swizzle bits
Make the values a bit more meaningful.
This commit is intentionally cross-subsystem to ease review, as the
patchset is intended to be merged together, with a maintainer
consensus.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/660981/
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index b34b1cbed350..d83133f39522 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -680,7 +680,7 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) BUG_ON(adreno_gpu->ubwc_config.highest_bank_bit < 13); u32 hbb = adreno_gpu->ubwc_config.highest_bank_bit - 13; bool rgb565_predicator = cfg->ubwc_enc_version >= UBWC_4_0; - u32 level2_swizzling_dis = !(cfg->ubwc_swizzle & BIT(1)); + u32 level2_swizzling_dis = !(cfg->ubwc_swizzle & UBWC_SWIZZLE_ENABLE_LVL2); bool ubwc_mode = qcom_ubwc_get_ubwc_mode(cfg); bool amsbc = cfg->ubwc_enc_version >= UBWC_3_0; bool min_acc_len_64b = false; |