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| author | Suraj Kandpal <suraj.kandpal@intel.com> | 2026-01-22 10:18:59 +0530 |
|---|---|---|
| committer | Suraj Kandpal <suraj.kandpal@intel.com> | 2026-01-27 08:33:35 +0530 |
| commit | bbde2759de1b85ae8c45281f251cdf61cd23fa7f (patch) | |
| tree | c34c085b9ad0f1c55683ef49076d12bd1b01e1ee /drivers/gpu | |
| parent | f86bed1bc93111a0308bc4d0335ee68d6fc9a1f4 (diff) | |
| download | linux-bbde2759de1b85ae8c45281f251cdf61cd23fa7f.tar.gz linux-bbde2759de1b85ae8c45281f251cdf61cd23fa7f.zip | |
drm/i915/cx0: Rename intel_clear_response_ready flag
Rename the non static intel_clear_response_ready_flag to
intel_cx0_clear_response_ready_flag so that we follow the
naming standards of non static function.
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Nemesa Garg <nemesa.garg@intel.com>
Link: https://patch.msgid.link/20260122044859.753682-2-suraj.kandpal@intel.com
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_cx0_phy.c | 14 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_cx0_phy.h | 4 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_lt_phy.c | 2 |
3 files changed, 10 insertions, 10 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index ff74f64eb970..6a471c021c0e 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -128,8 +128,8 @@ static void intel_cx0_phy_transaction_end(struct intel_encoder *encoder, struct intel_display_power_put(display, POWER_DOMAIN_DC_OFF, wakeref); } -void intel_clear_response_ready_flag(struct intel_encoder *encoder, - int lane) +void intel_cx0_clear_response_ready_flag(struct intel_encoder *encoder, + int lane) { struct intel_display *display = to_intel_display(encoder); @@ -156,7 +156,7 @@ void intel_cx0_bus_reset(struct intel_encoder *encoder, int lane) return; } - intel_clear_response_ready_flag(encoder, lane); + intel_cx0_clear_response_ready_flag(encoder, lane); } int intel_cx0_wait_for_ack(struct intel_encoder *encoder, @@ -223,7 +223,7 @@ static int __intel_cx0_read_once(struct intel_encoder *encoder, return -ETIMEDOUT; } - intel_clear_response_ready_flag(encoder, lane); + intel_cx0_clear_response_ready_flag(encoder, lane); intel_de_write(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane), XELPDP_PORT_M2P_TRANSACTION_PENDING | @@ -234,7 +234,7 @@ static int __intel_cx0_read_once(struct intel_encoder *encoder, if (ack < 0) return ack; - intel_clear_response_ready_flag(encoder, lane); + intel_cx0_clear_response_ready_flag(encoder, lane); /* * FIXME: Workaround to let HW to settle @@ -296,7 +296,7 @@ static int __intel_cx0_write_once(struct intel_encoder *encoder, return -ETIMEDOUT; } - intel_clear_response_ready_flag(encoder, lane); + intel_cx0_clear_response_ready_flag(encoder, lane); intel_de_write(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane), XELPDP_PORT_M2P_TRANSACTION_PENDING | @@ -326,7 +326,7 @@ static int __intel_cx0_write_once(struct intel_encoder *encoder, return -EINVAL; } - intel_clear_response_ready_flag(encoder, lane); + intel_cx0_clear_response_ready_flag(encoder, lane); /* * FIXME: Workaround to let HW to settle diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h index 347fdbc0af73..1d4480b8bf39 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h @@ -25,8 +25,8 @@ struct intel_dpll_hw_state; struct intel_encoder; struct intel_hdmi; -void intel_clear_response_ready_flag(struct intel_encoder *encoder, - int lane); +void intel_cx0_clear_response_ready_flag(struct intel_encoder *encoder, + int lane); bool intel_encoder_is_c10phy(struct intel_encoder *encoder); void intel_mtl_pll_enable(struct intel_encoder *encoder, struct intel_dpll *pll, diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c index b4b281ef258b..04f63bdd0b87 100644 --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c @@ -1053,7 +1053,7 @@ static int __intel_lt_phy_p2p_write_once(struct intel_encoder *encoder, * This is the time PHY takes to settle down after programming the PHY. */ udelay(150); - intel_clear_response_ready_flag(encoder, lane); + intel_cx0_clear_response_ready_flag(encoder, lane); intel_lt_phy_clear_status_p2p(encoder, lane); return 0; |