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| author | Tom St Denis <tom.stdenis@amd.com> | 2021-03-04 10:52:09 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2021-03-05 15:11:32 -0500 |
| commit | e49db376345290eeaed696557fa432b2420c7216 (patch) | |
| tree | 1a5e54d81b396beecf3c96e4670f61b0a68f68b6 /drivers/gpu | |
| parent | drm/amdgpu: add DMUB trace event IRQ source define (diff) | |
| download | linux-e49db376345290eeaed696557fa432b2420c7216.tar.gz linux-e49db376345290eeaed696557fa432b2420c7216.zip | |
drm/amd/amdgpu: Add missing BASE_IDX to dcn register
The register mmOTG1_OTG_BLANK_CONTROL was missing BASE_IDX value.
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h index cf166b591bc5..483769fb1736 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h @@ -8922,7 +8922,7 @@ #define mmOTG1_OTG_CONTROL 0x1bc1 #define mmOTG1_OTG_CONTROL_BASE_IDX 2 #define mmOTG1_OTG_BLANK_CONTROL 0x1bc2 -#define mmOTG1_OTG_BLANK_CONTROL_BASE_IDX +#define mmOTG1_OTG_BLANK_CONTROL_BASE_IDX 2 #define mmOTG1_OTG_INTERLACE_CONTROL 0x1bc4 #define mmOTG1_OTG_INTERLACE_CONTROL_BASE_IDX 2 #define mmOTG1_OTG_INTERLACE_STATUS 0x1bc5 |