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authorDikshita Agarwal <quic_dikshita@quicinc.com>2025-02-07 13:24:54 +0530
committerHans Verkuil <hverkuil@xs4all.nl>2025-02-07 11:51:30 +0100
commit33be1dde17e3e8b752d8ea8d7b1cd2504187fdae (patch)
tree0bc2d0c18d15ea62a4f4ed6f2ea6b0a9ebc2a915 /drivers/media/platform/qcom/iris/iris_platform_common.h
parentmedia: iris: implement subscribe_event and unsubscribe_event ioctls (diff)
downloadlinux-33be1dde17e3e8b752d8ea8d7b1cd2504187fdae.tar.gz
linux-33be1dde17e3e8b752d8ea8d7b1cd2504187fdae.zip
media: iris: implement iris v4l2_ctrl_ops
Initialize the control handler by reading the platform specific firmware capabilities. Capabilities are features, which are supported by a specific platform (SOC). Each capability is defined with a min, max, range and default value and a corresponding HFI. Implement s_ctrl and g_volatile_ctrl ctrl ops. Co-developed-by: Vedang Nagar <quic_vnagar@quicinc.com> Signed-off-by: Vedang Nagar <quic_vnagar@quicinc.com> Reviewed-by: Hans Verkuil <hverkuil@xs4all.nl> Tested-by: Stefan Schmidt <stefan.schmidt@linaro.org> # x1e80100 (Dell XPS 13 9345) Reviewed-by: Stefan Schmidt <stefan.schmidt@linaro.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-HDK Signed-off-by: Dikshita Agarwal <quic_dikshita@quicinc.com> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
Diffstat (limited to 'drivers/media/platform/qcom/iris/iris_platform_common.h')
-rw-r--r--drivers/media/platform/qcom/iris/iris_platform_common.h30
1 files changed, 30 insertions, 0 deletions
diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h
index 75d4932df910..23170cd37c04 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_common.h
+++ b/drivers/media/platform/qcom/iris/iris_platform_common.h
@@ -49,6 +49,34 @@ struct platform_inst_caps {
u32 max_frame_height;
u32 max_mbpf;
};
+
+enum platform_inst_fw_cap_type {
+ PROFILE = 1,
+ LEVEL,
+ DEBLOCK,
+ INST_FW_CAP_MAX,
+};
+
+enum platform_inst_fw_cap_flags {
+ CAP_FLAG_DYNAMIC_ALLOWED = BIT(0),
+ CAP_FLAG_MENU = BIT(1),
+ CAP_FLAG_INPUT_PORT = BIT(2),
+ CAP_FLAG_OUTPUT_PORT = BIT(3),
+ CAP_FLAG_CLIENT_SET = BIT(4),
+ CAP_FLAG_BITMASK = BIT(5),
+ CAP_FLAG_VOLATILE = BIT(6),
+};
+
+struct platform_inst_fw_cap {
+ enum platform_inst_fw_cap_type cap_id;
+ s64 min;
+ s64 max;
+ s64 step_or_mask;
+ s64 value;
+ u32 hfi_id;
+ enum platform_inst_fw_cap_flags flags;
+};
+
struct iris_core_power {
u64 clk_freq;
u64 icc_bw;
@@ -79,6 +107,8 @@ struct iris_platform_data {
const char *fwname;
u32 pas_id;
struct platform_inst_caps *inst_caps;
+ struct platform_inst_fw_cap *inst_fw_caps;
+ u32 inst_fw_caps_size;
struct tz_cp_config *tz_cp_config_data;
u32 core_arch;
u32 hw_response_timeout;