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authorDu, Changbin <changbin.du@intel.com>2016-01-18 21:02:42 +0800
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2016-01-24 21:06:21 -0800
commitd8f00cd685f5c8e0def8593e520a7fef12c22407 (patch)
tree5b6460db62b150678d1e7aab762ca40c2f041e1e /include/acpi/cppc_acpi.h
parentcdc-acm:exclude Samsung phone 04e8:685d (diff)
downloadlinux-d8f00cd685f5c8e0def8593e520a7fef12c22407.tar.gz
linux-d8f00cd685f5c8e0def8593e520a7fef12c22407.zip
usb: hub: do not clear BOS field during reset device
In function usb_reset_and_verify_device, the old BOS descriptor may still be used before allocating a new one. (usb_unlocked_disable_lpm function uses it under the situation that it fails to disable lpm.) So we cannot set the udev->bos to NULL before that, just keep what it was. It will be overwrite when allocating a new one. Crash log: BUG: unable to handle kernel NULL pointer dereference at 0000000000000010 IP: [<ffffffff8171f98d>] usb_enable_link_state+0x2d/0x2f0 Call Trace: [<ffffffff8171ed5b>] ? usb_set_lpm_timeout+0x12b/0x140 [<ffffffff8171fcd1>] usb_enable_lpm+0x81/0xa0 [<ffffffff8171fdd8>] usb_disable_lpm+0xa8/0xc0 [<ffffffff8171fe1c>] usb_unlocked_disable_lpm+0x2c/0x50 [<ffffffff81723933>] usb_reset_and_verify_device+0xc3/0x710 [<ffffffff8172c4ed>] ? usb_sg_wait+0x13d/0x190 [<ffffffff81724743>] usb_reset_device+0x133/0x280 [<ffffffff8179ccd1>] usb_stor_port_reset+0x61/0x70 [<ffffffff8179cd68>] usb_stor_invoke_transport+0x88/0x520 Signed-off-by: Du, Changbin <changbin.du@intel.com> Cc: stable <stable@vger.kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'include/acpi/cppc_acpi.h')
0 files changed, 0 insertions, 0 deletions
+1 Add a config for the MPSS present on SM6350. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211213082208.21492-3-luca.weiss@fairphone.com 2021-12-13dt-bindings: remoteproc: qcom: pas: Add SM6350 adsp, cdsp & mpssLuca Weiss1-0/+28 Add compatibles for the remoteprocs found in SM6350. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Acked-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211213082208.21492-2-luca.weiss@fairphone.com 2021-12-13remoteproc: qcom: pas: Add missing power-domain "mxc" for CDSPSibi Sankar1-0/+1 Add missing power-domain "mxc" required by CDSP PAS remoteproc on SM8350 SoC. Fixes: e8b4e9a21af7 ("remoteproc: qcom: pas: Add SM8350 PAS remoteprocs") Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Cc: stable@vger.kernel.org Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1624559605-29847-1-git-send-email-sibis@codeaurora.org 2021-12-13remoteproc: imx_rproc: correct firmware reloadPeng Fan1-3/+5 ENABLE_M4 should be set to 1 when loading code to TCM, otherwise you will not able to replace the firmware after you stop m4. Besides ENABLE_M4, we still need set SW_M4C_RST, because this bit will be automatically set with SW_M4C_NON_SCLR_RST set. Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210602064206.27004-1-peng.fan@oss.nxp.com 2021-12-13remoteproc: qcom: pil_info: Don't memcpy_toio more than is providedStephen Boyd1-1/+1 If the string passed into qcom_pil_info_store() isn't as long as PIL_RELOC_NAME_LEN we'll try to copy the string assuming the length is PIL_RELOC_NAME_LEN to the io space and go beyond the bounds of the string. Let's only copy as many byes as the string is long, ignoring the NUL terminator. This fixes the following KASAN error: BUG: KASAN: global-out-of-bounds in __memcpy_toio+0x124/0x140 Read of size 1 at addr ffffffd35086e386 by task rmtfs/2392 CPU: 2 PID: 2392 Comm: rmtfs Tainted: G W 5.16.0-rc1-lockdep+ #10 Hardware name: Google Lazor (rev3+) with KB Backlight (DT) Call trace: dump_backtrace+0x0/0x410 show_stack+0x24/0x30 dump_stack_lvl+0x7c/0xa0 print_address_description+0x78/0x2bc kasan_report+0x160/0x1a0 __asan_report_load1_noabort+0x44/0x50 __memcpy_toio+0x124/0x140 qcom_pil_info_store+0x298/0x358 [qcom_pil_info] q6v5_start+0xdf0/0x12e0 [qcom_q6v5_mss] rproc_start+0x178/0x3a0 rproc_boot+0x5f0/0xb90 state_store+0x78/0x1bc dev_attr_store+0x70/0x90 sysfs_kf_write+0xf4/0x118 kernfs_fop_write_iter+0x208/0x300 vfs_write+0x55c/0x804 ksys_pwrite64+0xc8/0x134 __arm64_compat_sys_aarch32_pwrite64+0xc4/0xdc invoke_syscall+0x78/0x20c el0_svc_common+0x11c/0x1f0 do_el0_svc_compat+0x50/0x60 el0_svc_compat+0x5c/0xec el0t_32_sync_handler+0xc0/0xf0 el0t_32_sync+0x1a4/0x1a8 The buggy address belongs to the variable: .str.59+0x6/0xffffffffffffec80 [qcom_q6v5_mss] Memory state around the buggy address: ffffffd35086e280: 00 00 00 00 02 f9 f9 f9 f9 f9 f9 f9 00 00 00 00 ffffffd35086e300: 00 02 f9 f9 f9 f9 f9 f9 00 00 00 06 f9 f9 f9 f9 >ffffffd35086e380: 06 f9 f9 f9 05 f9 f9 f9 00 00 00 00 00 06 f9 f9 ^ ffffffd35086e400: f9 f9 f9 f9 01 f9 f9 f9 04 f9 f9 f9 00 00 01 f9 ffffffd35086e480: f9 f9 f9 f9 00 00 00 00 00 00 00 01 f9 f9 f9 f9 Fixes: 549b67da660d ("remoteproc: qcom: Introduce helper to store pil info in IMEM") Signed-off-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211117065454.4142936-1-swboyd@chromium.org 2021-12-13remoteproc: Add Renesas rcar driverJulien Massot3-0/+236 Renesas Gen3 platform includes a Cortex-r7 processor. Both: the application cores (A5x) and the realtime core (CR7) share access to the RAM and devices with the same address map, so device addresses are equal to the Linux physical addresses. In order to initialize this remote processor we need to: - power on the realtime core - put the firmware in a RAM area - set the boot address for this firmware (reset vector) - Deassert the reset This initial driver allows to start and stop the Cortex R7 processor. Signed-off-by: Julien Massot <julien.massot@iot.bzh> Link: https://lore.kernel.org/r/20211207165829.195537-3-julien.massot@iot.bzh Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>