diff options
| author | Jon Hunter <jonathanh@nvidia.com> | 2016-03-30 10:15:15 +0100 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2016-04-29 17:17:47 +0200 |
| commit | a38045121bf42110e6043d07315a7626b021a0db (patch) | |
| tree | b3dc265025755ac39e69289443c2529d99e4fd15 /include/soc | |
| parent | dt-bindings: Add power domain info for NVIDIA PMC (diff) | |
| download | linux-a38045121bf42110e6043d07315a7626b021a0db.tar.gz linux-a38045121bf42110e6043d07315a7626b021a0db.zip | |
soc/tegra: pmc: Add generic PM domain support
Adds generic PM domain support to the PMC driver where the PM domains
are populated from device-tree and the PM domain consumer devices are
bound to their relevant PM domains via device-tree as well.
Update the tegra_powergate_sequence_power_up() API so that internally
it calls the same tegra_powergate_xxx functions that are used by the
Tegra generic PM domain code for consistency.
To ensure that the Tegra power domains (a.k.a. powergates) cannot be
controlled via both the legacy tegra_powergate_xxx functions as well
as the generic PM domain framework, add a bit map for available
powergates that can be controlled via the legacy powergate functions.
Move the majority of the tegra_powergate_remove_clamping() function
to a sub-function, so that this can be used by both the legacy and
generic power domain code.
This is based upon work by Thierry Reding <treding@nvidia.com>
and Vince Hsu <vinceh@nvidia.com>.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'include/soc')
| -rw-r--r-- | include/soc/tegra/pmc.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/soc/tegra/pmc.h b/include/soc/tegra/pmc.h index 07e332dd44fb..e9e53473a63e 100644 --- a/include/soc/tegra/pmc.h +++ b/include/soc/tegra/pmc.h @@ -72,6 +72,7 @@ int tegra_pmc_cpu_remove_clamping(unsigned int cpuid); #define TEGRA_POWERGATE_AUD 27 #define TEGRA_POWERGATE_DFD 28 #define TEGRA_POWERGATE_VE2 29 +#define TEGRA_POWERGATE_MAX TEGRA_POWERGATE_VE2 #define TEGRA_POWERGATE_3D0 TEGRA_POWERGATE_3D |