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| author | Daniel Vetter <daniel.vetter@ffwll.ch> | 2024-07-05 12:45:40 +0200 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2024-07-05 12:45:41 +0200 |
| commit | 62a05f4ae9c1fb70bc75d494c9c1c373d2c2e374 (patch) | |
| tree | c73b4354fb05179c295b233306a5d25664637579 /include/uapi | |
| parent | Merge tag 'drm-misc-next-2024-07-04' of https://gitlab.freedesktop.org/drm/mi... (diff) | |
| parent | dt-bindings: display/msm: dsi-controller-main: Add SM7150 (diff) | |
| download | linux-62a05f4ae9c1fb70bc75d494c9c1c373d2c2e374.tar.gz linux-62a05f4ae9c1fb70bc75d494c9c1c373d2c2e374.zip | |
Merge tag 'drm-msm-next-2024-07-04' of https://gitlab.freedesktop.org/drm/msm into drm-next
Updates for v6.11
Core:
- SM7150 support
DPU:
- SM7150 support
- Fix DSC support for DSI panels in video mode
- Fixed TE vsync source support for DSI command-mode panels
- Fix for devices without UBWC in the display controller (ie.
QCM2290)
DSI:
- Remove unused register-writing wrappers
- Fix DSC support for panels in video mode
- Add support for parsing TE vsync source
- Add support for MSM8937 (28nm DSI PHY)
MDP5:
- Add support for MSM8937
- Fix configuration for MSM8953
GPU:
- Split giant device table into per-gen "hw catalog" similar to
what is done on the display side of the driver
- Fix a702 UBWC mode
- Fix unused variably warnings
- GPU memory traces
- Add param for userspace to know if raytracing is supported
- Memory barrier cleanup and GBIF unhalt fix
- X185 support (aka gpu in X1 laptop chips)
- a505 support
- fixes
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
From: Rob Clark <robdclark@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/CAF6AEGvZQpYEHpSCgXGJ2kaHJDK6QFAFfTsfiWm4b2zZOnjXGw@mail.gmail.com
Diffstat (limited to 'include/uapi')
| -rw-r--r-- | include/uapi/drm/msm_drm.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/uapi/drm/msm_drm.h b/include/uapi/drm/msm_drm.h index d8a6b3472760..3fca72f73861 100644 --- a/include/uapi/drm/msm_drm.h +++ b/include/uapi/drm/msm_drm.h @@ -87,6 +87,7 @@ struct drm_msm_timespec { #define MSM_PARAM_VA_START 0x0e /* RO: start of valid GPU iova range */ #define MSM_PARAM_VA_SIZE 0x0f /* RO: size of valid GPU iova range (bytes) */ #define MSM_PARAM_HIGHEST_BANK_BIT 0x10 /* RO */ +#define MSM_PARAM_RAYTRACING 0x11 /* RO */ /* For backwards compat. The original support for preemption was based on * a single ring per priority level so # of priority levels equals the # |