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| author | Stephen Boyd <sboyd@kernel.org> | 2025-09-21 09:56:03 -0700 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2025-09-21 09:56:03 -0700 |
| commit | 1803012a8929213b1abb9a46fc92de3674187085 (patch) | |
| tree | 24c01fcc28b8f32f613be1c1619d3d90bea80944 /include | |
| parent | Linux 6.17-rc1 (diff) | |
| parent | ARM: at91: remove default values for PMC_PLL_ACR (diff) | |
| download | linux-1803012a8929213b1abb9a46fc92de3674187085.tar.gz linux-1803012a8929213b1abb9a46fc92de3674187085.zip | |
Merge tag 'clk-microchip-6.18-2' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into clk-microchip
Pull Microchip clk driver updates from Nicolas Ferre:
- add one clock for sam9x75
- new meaning for MCR register field in clk-master
- use force-write to PLL update register to ensure
reliable programming sequence
- update Analog Control Register (ACR) management to accommodate
differences across SoCs.
- ACR management dependency with one ARM PM patch added beforehand
* tag 'clk-microchip-6.18-2' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux:
ARM: at91: remove default values for PMC_PLL_ACR
clk: at91: add ACR in all PLL settings
clk: at91: sam9x7: Add peripheral clock id for pmecc
clk: at91: clk-master: Add check for divide by 3
clk: at91: clk-sam9x60-pll: force write to PLL_UPDT register
ARM: at91: pm: save and restore ACR during PLL disable/enable
Diffstat (limited to 'include')
| -rw-r--r-- | include/linux/clk/at91_pmc.h | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/include/linux/clk/at91_pmc.h b/include/linux/clk/at91_pmc.h index 7af499bdbecb..d60ce9708ea2 100644 --- a/include/linux/clk/at91_pmc.h +++ b/include/linux/clk/at91_pmc.h @@ -47,8 +47,6 @@ #define AT91_PMC_PCSR 0x18 /* Peripheral Clock Status Register */ #define AT91_PMC_PLL_ACR 0x18 /* PLL Analog Control Register [for SAM9X60] */ -#define AT91_PMC_PLL_ACR_DEFAULT_UPLL UL(0x12020010) /* Default PLL ACR value for UPLL */ -#define AT91_PMC_PLL_ACR_DEFAULT_PLLA UL(0x00020010) /* Default PLL ACR value for PLLA */ #define AT91_PMC_PLL_ACR_UTMIVR (1 << 12) /* UPLL Voltage regulator Control */ #define AT91_PMC_PLL_ACR_UTMIBG (1 << 13) /* UPLL Bandgap Control */ |