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| author | Marc Zyngier <maz@kernel.org> | 2026-02-05 09:17:30 +0000 |
|---|---|---|
| committer | Marc Zyngier <maz@kernel.org> | 2026-02-05 09:17:30 +0000 |
| commit | 47e89febd3f5cf52b672f0841b42ac67610ef87a (patch) | |
| tree | 8b8893eef8ba915cd0ee3c77a78395cef75a1bdf /include | |
| parent | 1c880ea3efd77ce1a3e16aeb617fdd76d28e197a (diff) | |
| parent | 3227c3a89d65fe7482312b7b27038d9ebd86f210 (diff) | |
| download | linux-47e89febd3f5cf52b672f0841b42ac67610ef87a.tar.gz linux-47e89febd3f5cf52b672f0841b42ac67610ef87a.zip | |
Merge branch kvm-arm64/gicv5-prologue into kvmarm-master/next
* kvm-arm64/gicv5-prologue:
: .
: Prologue to GICv5 support, courtesy of Sascha Bischoff.
:
: This is preliminary work that sets the scene for the full-blow
: support.
: .
irqchip/gic-v5: Check if impl is virt capable
KVM: arm64: gic: Set vgic_model before initing private IRQs
arm64/sysreg: Drop ICH_HFGRTR_EL2.ICC_HAPR_EL1 and make RES1
KVM: arm64: gic-v3: Switch vGIC-v3 to use generated ICH_VMCR_EL2
Signed-off-by: Marc Zyngier <maz@kernel.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/linux/irqchip/arm-gic-v5.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/include/linux/irqchip/arm-gic-v5.h b/include/linux/irqchip/arm-gic-v5.h index 68ddcdb1cec5..4cb71ce6e8ad 100644 --- a/include/linux/irqchip/arm-gic-v5.h +++ b/include/linux/irqchip/arm-gic-v5.h @@ -43,6 +43,7 @@ /* * IRS registers and tables structures */ +#define GICV5_IRS_IDR0 0x0000 #define GICV5_IRS_IDR1 0x0004 #define GICV5_IRS_IDR2 0x0008 #define GICV5_IRS_IDR5 0x0014 @@ -63,6 +64,8 @@ #define GICV5_IRS_IST_STATUSR 0x0194 #define GICV5_IRS_MAP_L2_ISTR 0x01c0 +#define GICV5_IRS_IDR0_VIRT BIT(6) + #define GICV5_IRS_IDR1_PRIORITY_BITS GENMASK(22, 20) #define GICV5_IRS_IDR1_IAFFID_BITS GENMASK(19, 16) @@ -278,6 +281,7 @@ struct gicv5_chip_data { u8 cpuif_pri_bits; u8 cpuif_id_bits; u8 irs_pri_bits; + bool virt_capable; struct { __le64 *l1ist_addr; u32 l2_size; |