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| author | Rafael J. Wysocki <rafael.j.wysocki@intel.com> | 2025-09-11 18:08:45 +0200 |
|---|---|---|
| committer | Rafael J. Wysocki <rafael.j.wysocki@intel.com> | 2025-09-11 18:08:45 +0200 |
| commit | 531453a36c1391445fffa5721c1153c9f2d64eeb (patch) | |
| tree | 278622f7ead47feaf252d8677cd4fe5aed03a9c8 /include | |
| parent | Linux 6.17-rc5 (diff) | |
| parent | PM / devfreq: rockchip-dfi: add support for LPDDR5 (diff) | |
| download | linux-531453a36c1391445fffa5721c1153c9f2d64eeb.tar.gz linux-531453a36c1391445fffa5721c1153c9f2d64eeb.zip | |
Merge tag 'devfreq-next-for-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/chanwoo/linux
Merge devfreq updates for v6.18 from Chanwoo Choi:
"- Add support for LPDDR5 for Rockhip RK3588 SoC on rockchip-dfi devfreq
driver.
- Fix an issue where DDR cycle counts on RK3588/RK3528 with LPDDR4(X)
are reported as half by adding a cycle multiplier to the DFI driver
on rockchip-dfi devfreq-event driver.
- Fix missing error pointer dereference of regulator instance
and remove redundant condition on on mtk-cci-devfreq.c devfreq
driver."
* tag 'devfreq-next-for-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/chanwoo/linux:
PM / devfreq: rockchip-dfi: add support for LPDDR5
PM / devfreq: rockchip-dfi: double count on RK3588
PM / devfreq: mtk-cci: avoid redundant conditions
PM / devfreq: mtk-cci: Fix potential error pointer dereference in probe()
Diffstat (limited to 'include')
| -rw-r--r-- | include/soc/rockchip/rk3588_grf.h | 8 | ||||
| -rw-r--r-- | include/soc/rockchip/rockchip_grf.h | 1 |
2 files changed, 7 insertions, 2 deletions
diff --git a/include/soc/rockchip/rk3588_grf.h b/include/soc/rockchip/rk3588_grf.h index 630b35a55064..02a7b2432d99 100644 --- a/include/soc/rockchip/rk3588_grf.h +++ b/include/soc/rockchip/rk3588_grf.h @@ -12,7 +12,11 @@ #define RK3588_PMUGRF_OS_REG3_DRAMTYPE_INFO_V3 GENMASK(13, 12) #define RK3588_PMUGRF_OS_REG3_SYSREG_VERSION GENMASK(31, 28) -#define RK3588_PMUGRF_OS_REG4 0x210 -#define RK3588_PMUGRF_OS_REG5 0x214 +#define RK3588_PMUGRF_OS_REG4 0x210 +#define RK3588_PMUGRF_OS_REG5 0x214 +#define RK3588_PMUGRF_OS_REG6 0x218 +#define RK3588_PMUGRF_OS_REG6_LP5_BANK_MODE GENMASK(2, 1) +/* Whether the LPDDR5 is in 2:1 (= 0) or 4:1 (= 1) CKR a.k.a. DQS mode */ +#define RK3588_PMUGRF_OS_REG6_LP5_CKR BIT(0) #endif /* __SOC_RK3588_GRF_H */ diff --git a/include/soc/rockchip/rockchip_grf.h b/include/soc/rockchip/rockchip_grf.h index e46fd72aea8d..41c7bb26fd53 100644 --- a/include/soc/rockchip/rockchip_grf.h +++ b/include/soc/rockchip/rockchip_grf.h @@ -13,6 +13,7 @@ enum { ROCKCHIP_DDRTYPE_LPDDR3 = 6, ROCKCHIP_DDRTYPE_LPDDR4 = 7, ROCKCHIP_DDRTYPE_LPDDR4X = 8, + ROCKCHIP_DDRTYPE_LPDDR5 = 9, }; #endif /* __SOC_ROCKCHIP_GRF_H */ |