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| author | Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> | 2026-02-02 15:12:02 +0530 |
|---|---|---|
| committer | Suraj Kandpal <suraj.kandpal@intel.com> | 2026-02-10 11:03:13 +0530 |
| commit | 55c19e27c56d7843afd08634114d510f67f75370 (patch) | |
| tree | 9005fa579065300524649350b257585ea734655f /include | |
| parent | 3c2d28f4a67af7ada8f3332270b0d349967e6aa1 (diff) | |
| download | linux-55c19e27c56d7843afd08634114d510f67f75370.tar.gz linux-55c19e27c56d7843afd08634114d510f67f75370.zip | |
drm/i915/color: Add failure handling in plane color pipeline init
The plane color pipeline initialization built up multiple colorop blocks
inline, but did not reliably clean up partially constructed pipelines
when an intermediate step failed. This could lead to leaked colorop
objects and fragile error handling as the pipeline grows.
Refactor the pipeline construction to use a common helper for adding
colorop blocks. This centralizes allocation, initialization, and
teardown logic, allowing the caller to reliably unwind all previously
created colorops on failure.
v2:
- Refactor code to avoid repetition (Suraj)
v3:
- s/nvl/xe3plpd (Suraj)
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Acked-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://patch.msgid.link/20260202094202.2871478-10-chaitanya.kumar.borah@intel.com
Diffstat (limited to 'include')
0 files changed, 0 insertions, 0 deletions