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authorTomeu Vizoso <tomeu.vizoso@collabora.com>2016-09-01 09:41:35 +0200
committerDaniel Vetter <daniel.vetter@ffwll.ch>2016-09-01 10:41:53 +0200
commit75ac49532a3cd44f2b22d88bab888ae92c411650 (patch)
treed0ecf5691c4c19a40a88e0d1b7beebad4731ff84 /scripts/stackusage
parentRevert "drm: make DRI1 drivers depend on BROKEN" (diff)
downloadlinux-75ac49532a3cd44f2b22d88bab888ae92c411650.tar.gz
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drm/doc: Add a few words on validation with IGT
Also provide some pointers for building IGT as some kernel hackers might not be that familiar with building stuff on Linux distros. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Cc: Daniel Vetter <daniel.vetter@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1472715695-19812-1-git-send-email-tomeu.vizoso@collabora.com
Diffstat (limited to 'scripts/stackusage')
0 files changed, 0 insertions, 0 deletions
>Paul Mundt1-2/+2 2008-01-28sh: Split out extable.c _32 and _64 variants.Paul Mundt5-36/+52 2008-01-28sh: Add SH-5 support to the consistent DMA impl.Paul Mundt2-20/+30 2008-01-28sh: flush_cache_sigtramp() takes 1 arg only.Paul Mundt1-1/+1 2008-01-28sh: Move vsyscall_init() defs up one level.Paul Mundt2-6/+6 2008-01-28sh: Nopped out p3_cache_init() on SH-5 also.Paul Mundt1-0/+1 2008-01-28sh: Fix up VMALLOC_START for SH-5.Paul Mundt1-0/+4 2008-01-28sh: Move over the SH-5 head.S and tlb.h.Paul Mundt6-44/+24 2008-01-28sh: Have SH-5 provide an {en,dis}able_fpu() impl.Paul Mundt3-10/+21 2008-01-28sh: Disable initial cache flush on SH-5.Paul Mundt1-14/+18 2008-01-28sh: Don't reference UBC code in CPU init on sh64.Paul Mundt1-1/+6 2008-01-28sh: imask IRQ depends on sh32.Paul Mundt1-1/+2 2008-01-28sh: Move in the SH-5 traps.c impl.Paul Mundt4-3/+2