aboutsummaryrefslogtreecommitdiffstats
path: root/tools/include
diff options
context:
space:
mode:
authorLorenzo Stoakes <lorenzo.stoakes@oracle.com>2025-08-11 06:26:54 +0100
committerAndrew Morton <akpm@linux-foundation.org>2025-08-19 16:35:54 -0700
commit9a6a6a3191574a01dcf7a7d9385246d7bc8736bc (patch)
tree72eaf2cd9c4f8b4d4fa87287389bc2272d5da4e3 /tools/include
parentmm/debug_vm_pgtable: clear page table entries at destroy_args() (diff)
downloadlinux-9a6a6a3191574a01dcf7a7d9385246d7bc8736bc.tar.gz
linux-9a6a6a3191574a01dcf7a7d9385246d7bc8736bc.zip
tools/testing: add linux/args.h header and fix radix, VMA tests
Commit 857d18f23ab1 ("cleanup: Introduce ACQUIRE() and ACQUIRE_ERR() for conditional locks") accidentally broke the radix tree, VMA userland tests by including linux/args.h which is not present in the tools/include directory. This patch copies this over and adds an #ifdef block to avoid duplicate __CONCAT declaration in conflict with system headers when we ultimately include this. Link: https://lkml.kernel.org/r/20250811052654.33286-1-lorenzo.stoakes@oracle.com Fixes: 857d18f23ab1 ("cleanup: Introduce ACQUIRE() and ACQUIRE_ERR() for conditional locks") Signed-off-by: Lorenzo Stoakes <lorenzo.stoakes@oracle.com> Cc: Jann Horn <jannh@google.com> Cc: John Hubbard <jhubbard@nvidia.com> Cc: Liam Howlett <liam.howlett@oracle.com> Cc: Sidhartha Kumar <sidhartha.kumar@oracle.com> Cc: Vlastimil Babka <vbabka@suse.cz> Cc: Dan Williams <dan.j.williams@intel.com> Cc: Peter Zijlstra <peterz@infradead.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Diffstat (limited to 'tools/include')
-rw-r--r--tools/include/linux/args.h28
1 files changed, 28 insertions, 0 deletions
diff --git a/tools/include/linux/args.h b/tools/include/linux/args.h
new file mode 100644
index 000000000000..2e8e65d975c7
--- /dev/null
+++ b/tools/include/linux/args.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef _LINUX_ARGS_H
+#define _LINUX_ARGS_H
+
+/*
+ * How do these macros work?
+ *
+ * In __COUNT_ARGS() _0 to _12 are just placeholders from the start
+ * in order to make sure _n is positioned over the correct number
+ * from 12 to 0 (depending on X, which is a variadic argument list).
+ * They serve no purpose other than occupying a position. Since each
+ * macro parameter must have a distinct identifier, those identifiers
+ * are as good as any.
+ *
+ * In COUNT_ARGS() we use actual integers, so __COUNT_ARGS() returns
+ * that as _n.
+ */
+
+/* This counts to 15. Any more, it will return 16th argument. */
+#define __COUNT_ARGS(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, _11, _12, _13, _14, _15, _n, X...) _n
+#define COUNT_ARGS(X...) __COUNT_ARGS(, ##X, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0)
+
+/* Concatenate two parameters, but allow them to be expanded beforehand. */
+#define __CONCAT(a, b) a ## b
+#define CONCATENATE(a, b) __CONCAT(a, b)
+
+#endif /* _LINUX_ARGS_H */
630&follow=1'>clk: bcm: rpi: Turn firmware clock on/off when preparing/unpreparingMaíra Canal1-1/+55 Currently, when we prepare or unprepare RPi's clocks, we don't actually enable/disable the firmware clock. This means that `clk_disable_unprepare()` doesn't actually change the clock state at all, nor does it lowers the clock rate. From the Mailbox Property Interface documentation [1], we can see that we should use `RPI_FIRMWARE_SET_CLOCK_STATE` to set the clock state off/on. Therefore, use `RPI_FIRMWARE_SET_CLOCK_STATE` to create a prepare and an unprepare hook for RPi's firmware clock. As now the clocks are actually turned off, some of them are now marked CLK_IS_CRITICAL, as those are required to be on during the whole system operation. Link: https://github.com/raspberrypi/firmware/wiki/Mailbox-property-interface [1] Signed-off-by: Maíra Canal <mcanal@igalia.com> Reviewed-by: Stefan Wahren <wahrenst@gmx.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org> 2025-09-21clk: bcm: rpi: Add missing logs if firmware failsStefan Wahren1-2/+8 In contrary to raspberrypi_fw_set_rate(), the ops for is_prepared() and recalc_rate() silently ignore firmware errors by just returning 0. Since these operations should never fail, add at least error logs to inform the user. Signed-off-by: Stefan Wahren <wahrenst@gmx.net> Signed-off-by: Maíra Canal <mcanal@igalia.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org> 2025-09-19clk: spacemit: fix i2s clockTroy Mitchell2-2/+27 Defining i2s_bclk and i2s_sysclk as fixed-rate clocks is insufficient for real I2S use cases. Moreover, the current I2S clock configuration does not work as expected due to missing parent clocks. This patch adds the missing parent clocks, defines i2s_sysclk as a DDN clock, and i2s_bclk as a DIV clock. A special note for i2s_bclk: From the register definition, the i2s_bclk divider always implies an additional 1/2 factor. The following table shows the correspondence between index and frequency division coefficients: | index | div | |-------|-------| | 0 | 2 | | 1 | 4 | | 2 | 6 | | 3 | 8 | From a software perspective, introducing i2s_bclk_factor as the parent of i2s_bclk is sufficient to address the issue. The I2S-related clock registers can be found here [1]. Link: https://developer.spacemit.com/documentation?token=LCrKwWDasiJuROkVNusc2pWTnEb [1] Fixes: 1b72c59db0add ("clk: spacemit: Add clock support for SpacemiT K1 SoC") Co-developer: Jinmei Wei <weijinmei@linux.spacemit.com> Suggested-by: Haylen Chu <heylenay@4d2.org> Signed-off-by: Jinmei Wei <weijinmei@linux.spacemit.com> Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org> 2025-09-19clk: spacemit: introduce pre-div for ddn clockTroy Mitchell3-10/+12 The original DDN operations applied an implicit divide-by-2, which should not be a default behavior. This patch removes that assumption, letting each clock define its actual behavior explicitly. Reviewed-by: Haylen Chu <heylenay@4d2.org> Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org> 2025-09-19dt-bindings: clock: spacemit: introduce i2s pre-clock to fix i2s clockTroy Mitchell1-0/+4 Previously, the K1 clock driver did not include the parent clocks of the I2S sysclk. Introduce pre-clock to fix I2S clock. Otherwise, the I2S clock may not work as expected. This patch adds their definitions to allow proper registration in the driver and usage in the device tree. Fixes: 1b72c59db0add ("clk: spacemit: Add clock support for SpacemiT K1 SoC") Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org> 2025-09-19clk: scmi: Add duty cycle ops only when duty cycle is supportedJacky Bai1-2/+9 For some of the SCMI based platforms, the oem extended config may be supported, but not for duty cycle purpose. Skip the duty cycle ops if err return when trying to get duty cycle info. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org> 2025-09-19dt-bindings: clock: mediatek: Add power-domains propertyJulien Massot1-0/+15 The mt8183-mfgcfg node uses a power domain in its device tree node. To prevent schema validation warnings, add the optional `power-domains` property to the binding schema for mediatek syscon clocks. Fixes: 1781f2c46180 ("arm64: dts: mediatek: mt8183: Add power-domains properity to mfgcfg") Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Julien Massot <julien.massot@collabora.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> 2025-09-19clk: keystone: sci-clk: use devm_kmemdup_array()Raag Jadav1-4/+1 Convert to use devm_kmemdup_array() which is more robust. Signed-off-by: Raag Jadav <raag.jadav@intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Nishanth Menon <nm@ti.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org> 2025-09-19clk: ti: am33xx: keep WKUP_DEBUGSS_CLKCTRL enabledMatthias Schiffer1-0/+2 As described in AM335x Errata Advisory 1.0.42, WKUP_DEBUGSS_CLKCTRL can't be disabled - the clock module will just be stuck in transitioning state forever, resulting in the following warning message after the wait loop times out: l3-aon-clkctrl:0000:0: failed to disable Just add the clock to enable_init_clks, so no attempt is made to disable it. Signed-off-by: Matthias Schiffer <matthias.schiffer@tq-group.com> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Acked-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org> 2025-09-19clk: amlogic: fix recent code refactoringMarek Szyprowski1-1/+1 Commit 4c4e17f27013 ("clk: amlogic: naming consistency alignment") refactored some internals in the g12a meson clock driver. Unfortunately it introduced a bug in the clock init data, which results in the following kernel panic: Unable to handle kernel NULL pointer dereference at virtual address 0000000000000000 Mem abort info: ... Data abort info: ... [0000000000000000] user address but active_mm is swapper Internal error: Oops: 0000000096000004 [#1] SMP Modules linked in: CPU: 4 UID: 0 PID: 1 Comm: swapper/0 Not tainted 6.17.0-rc1+ #11158 PREEMPT Hardware name: Hardkernel ODROID-N2 (DT) pstate: 60000005 (nZCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--) pc : __clk_register+0x60/0x92c lr : __clk_register+0x48/0x92c ... Call trace: __clk_register+0x60/0x92c (P) devm_clk_hw_register+0x5c/0xd8 meson_eeclkc_probe+0x74/0x110 g12a_clkc_probe+0x2c/0x58 platform_probe+0x5c/0xac really_probe+0xbc/0x298 __driver_probe_device+0x78/0x12c driver_probe_device+0xdc/0x164 __driver_attach+0x9c/0x1ac bus_for_each_dev+0x74/0xd0 driver_attach+0x24/0x30 bus_add_driver+0xe4/0x208 driver_register+0x60/0x128 __platform_driver_register+0x24/0x30 g12a_clkc_driver_init+0x1c/0x28 do_one_initcall+0x64/0x308 kernel_init_freeable+0x27c/0x4f8 kernel_init+0x20/0x1d8 ret_from_fork+0x10/0x20 Code: 52800038 aa0003fc b9010018 52819801 (f9400260) ---[ end trace 0000000000000000 ]--- Fix this by correcting the clock init data. Fixes: 4c4e17f27013 ("clk: amlogic: naming consistency alignment") Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on BananPi M2S Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org> 2025-09-16dt-bindings: clock: silabs,si5341: Add missing propertiesRob Herring (Arm)1-0/+6 Add "clock-output-names" which is a standard property for clock providers. Add the "always-on" boolean property which was undocumented, but already in use for some time. The flag prevents a clock output from being disabled. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Tested-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Michal Simek <michal.simek@amd.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org> 2025-09-14clk: tegra: dfll: Add CVB tables for Tegra114Svyatoslav Ryhel2-28/+132 Extend the Tegra124 DFLL driver to include configuration settings required for Tegra114 compatibility. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> [treding@nvidia.com: Use TEGRA210 instead of T210] Signed-off-by: Thierry Reding <treding@nvidia.com> 2025-09-13clk: sunxi-ng: add support for the A523/T527 MCU CCUChen-Yu Tsai3-0/+476 The A523/T527 SoCs have a new MCU PRCM, which has more clocks and reset controls for the RISC-V MCU and other peripherals. There is a second audio PLL, but no bus clock dividers. The BSP driver uses the 24MHz main oscillator as the parent for all the bus clocks. But the diagram suggests busses from the other PRCM are used in this block as well. Add a driver to support this part. Unlike the BSP driver, the SoC's main MBUS clock is chosen as the parent for the MCU MBUS clock, and the latter then serves as the parent of the MCU DMA controller's MBUS clock. The bus gate clocks also use their respective bus clocks as parents according to the system bus tree diagram. In cases where a block does not appear in that diagram, an educated guess is made. Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20250911174710.3149589-6-wens@kernel.org Signed-off-by: Chen-Yu Tsai <wens@csie.org> 2025-09-13clk: sunxi-ng: div: support power-of-two dividersChen-Yu Tsai1-0/+18 Some clocks (for timers) on the A523 are mux-divider-gate types with the divider being values of power-of-two. Add a macro for these types of clocks so that we can use the divider types instead of the M-P types without an M divider. Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20250911174710.3149589-5-wens@kernel.org Signed-off-by: Chen-Yu Tsai <wens@csie.org> 2025-09-13clk: sunxi-ng: sun55i-a523-ccu: Add missing NPU module clockChen-Yu Tsai2-17/+18 The main clock controller on the A523/T527 has the NPU's module clock. It was missing from the original submission, likely because that was based on the A523 user manual; the A523 is marketed without the NPU. Also, merge the private header back into the driver code itself. The header only contains a macro containing the total number of clocks. This has to be updated every time a missing clock gets added. Having it in a separate file doesn't help the process. Instead just drop the macro, and thus the header no longer has any reason to exist. Also move the .num value to after the list of clks to make it obvious that it should be updated when new clks are added. Reviewed-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20250911174710.3149589-4-wens@kernel.org Signed-off-by: Chen-Yu Tsai <wens@csie.org> 2025-09-13dt-bindings: clock: sun55i-a523-ccu: Add A523 MCU CCU clock controllerChen-Yu Tsai3-2/+119 There are four clock controllers in the A523 SoC. The existing binding already covers two of them that are critical for basic operation. The remaining ones are the MCU clock controller and CPU PLL clock controller. Add a description for the MCU CCU. This unit controls and provides clocks to the MCU (RISC-V) subsystem and peripherals meant to operate under low power conditions. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20250911174710.3149589-3-wens@kernel.org Signed-off-by: Chen-Yu Tsai <wens@csie.org> 2025-09-13dt-bindings: clock: sun55i-a523-ccu: Add missing NPU module clockChen-Yu Tsai1-0/+1 The main clock controller on the A523/T527 has the NPU's module clock. It was missing from the original submission, likely because that was based on the A523 user manual; the A523 is marketed without the NPU. Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20250911174710.3149589-2-wens@kernel.org Signed-off-by: Chen-Yu Tsai <wens@csie.org> 2025-09-12clk: imx95-blk-ctl: Save/restore registers when RPM routines are calledLaurentiu Palcu1-12/+21 When runtime PM is used for clock providers that are part of a power domain, the power domain supply is cut off during runtime suspend. This causes all BLK CTL registers belonging to that power domain to reset. To prevent this, save the state of the registers before entering suspend and restore them on resume. Additionally, disable the APB clock during suspend to minimize power consumption. Signed-off-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20250804131450.3918846-3-laurentiu.palcu@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org> 2025-09-12clk: imx95-blk-ctl: Save platform data in imx95_blk_ctl structureLaurentiu Palcu1-23/+13 Add a platform data (pdata) member to struct imx95_blk_ctl to store the result of of_device_get_match_data() during probe to avoid redundant calls in suspend and resume functions. Signed-off-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20250804131450.3918846-2-laurentiu.palcu@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org> 2025-09-12clk: renesas: r9a09g05[67]: Reduce differencesGeert Uytterhoeven2-6/+5 The clock drivers for RZ/V2H and RZ/V2N are very similar. Reduce the differences between them by: - Moving and reformatting the PLLCM33_GEAR clock definitions, - Replacing spaces by TABs. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/2246d2263e8a24d1aaf653db2004cbf2263c9048.1757606097.git.geert+renesas@glider.be 2025-09-12clk: renesas: r9a09g047: Add USB3.0 clocks/resetsBiju Das1-1/+8 Add USB3.0 clock and reset entries. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20250909180803.140939-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> 2025-09-12clk: renesas: cpg-mssr: Fix memory leak in cpg_mssr_reserved_init()Yuan CHen1-2/+5 In case of krealloc_array() failure, the current error handling just returns from the function without freeing the original array. Fix this memory leak by freeing the original array. Fixes: 6aa1754764901668 ("clk: renesas: cpg-mssr: Ignore all clocks assigned to non-Linux system") Signed-off-by: Yuan CHen <chenyuan@kylinos.cn> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20250908012810.4767-1-chenyuan_fl@163.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> 2025-09-11clk: qcom: gcc-sc8280xp: drop obsolete PCIe GDSC commentJohan Hovold1-4/+0 Drop an obsolete comment about keeping the PCIe GDSCs always-on, something which is no longer the case since commit db382dd55bcb ("clk: qcom: gcc-sc8280xp: Allow PCIe GDSCs to enter retention state"). Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250910134737.19381-1-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson <andersson@kernel.org> 2025-09-11clk: qcom: tcsrcc-x1e80100: Set the bi_tcxo as parent to eDP refclkAbel Vesa1-0/+4 All the other ref clocks provided by this driver have the bi_tcxo as parent. The eDP refclk is the only one without a parent, leading to reporting its rate as 0. So set its parent to bi_tcxo, just like the rest of the refclks. Cc: stable@vger.kernel.org # v6.9 Fixes: 06aff116199c ("clk: qcom: Add TCSR clock driver for x1e80100") Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250730-clk-qcom-tcsrcc-x1e80100-parent-edp-refclk-v1-1-7a36ef06e045@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org> 2025-09-12clk: sunxi-ng: sun6i-rtc: Add A523 specificsChen-Yu Tsai1-0/+11 The A523's RTC block is backward compatible with the R329's, but it also has a calibration function for its internal oscillator, which would allow it to provide a clock rate closer to the desired 32.768 KHz. This is useful on the Radxa Cubie A5E, which does not have an external 32.768 KHz crystal. Add new compatible-specific data for it. Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20250909170947.2221611-1-wens@kernel.org Signed-off-by: Chen-Yu Tsai <wens@csie.org> 2025-09-11clk: renesas: r9a09g056: Add clock and reset entries for I3CLad Prabhakar1-0/+8 Add module clock entries for the I3C controller on the RZ/V2N (R9A09G056) SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20250904155507.245744-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> 2025-09-11clk: renesas: r9a09g057: Add clock and reset entries for I3CLad Prabhakar1-0/+8 Add module clock entries for the I3C controller on the RZ/V2H(P) (R9A09G057) SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20250904155507.245744-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> 2025-09-11dt-bindings: clock: renesas,r9a09g047-cpg: Add USB3.0 core clocksBiju Das1-0/+2 Add definitions for USB3.0 core clocks in the R9A09G047 CPG DT bindings header file. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://patch.msgid.link/20250909180803.140939-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> 2025-09-11clk: tegra: Add DFLL DVCO reset control for Tegra114Svyatoslav Ryhel2-6/+26 The DVCO present in the DFLL IP block has a separate reset line, exposed via the CAR IP block. This reset line is asserted upon SoC reset. Unless something (such as the DFLL driver) deasserts this line, the DVCO will not oscillate, although reads and writes to the DFLL IP block will complete. Based on a3c83ff2 ("clk: tegra: Add DFLL DVCO reset control for Tegra124") Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> 2025-09-11dt-bindings: arm: tegra: Add ASUS TF101G and SL101Svyatoslav Ryhel1-2/+6 Add a compatible for ASUS Eee Pad Transformer TF101G and ASUS Eee Pad Slider SL101. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>