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authorMichael Neuling <mikey@neuling.org>2026-04-09 09:11:39 +0000
committerPaul Walmsley <pjw@kernel.org>2026-04-30 20:00:14 -0600
commit4d2b03699460b8fd5df34408a03a84a1a7ff8aa1 (patch)
tree706d19a573155d87f01d3428f5d6ecf518919a5a /tools/lib/python/__init__.py
parenta2e5b58811c7bb7d63f366f586cc7317f20e62e7 (diff)
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riscv: errata: Fix bitwise vs logical AND in MIPS errata patching
The condition checking whether a specific errata needs patching uses logical AND (&&) instead of bitwise AND (&). Since logical AND only checks that both operands are non-zero, this causes all errata patches to be applied whenever any single errata is detected, rather than only applying the matching one. The SiFive errata implementation correctly uses bitwise AND for the same check. Fixes: 0b0ca959d206 ("riscv: errata: Fix the PAUSE Opcode for MIPS P8700") Signed-off-by: Michael Neuling <mikey@neuling.org> Assisted-by: Cursor:claude-4.6-opus-high-thinking Link: https://patch.msgid.link/20260409091143.1348853-2-mikey@neuling.org [pjw@kernel.org: fixed checkpatch warning] Signed-off-by: Paul Walmsley <pjw@kernel.org>
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