diff options
| author | Sean Christopherson <seanjc@google.com> | 2022-07-11 23:27:49 +0000 |
|---|---|---|
| committer | Sean Christopherson <seanjc@google.com> | 2022-07-13 18:14:06 -0700 |
| commit | 2626206963ace9e8bf92b6eea5ff78dd674c555c (patch) | |
| tree | dd1a5b75a9141a9ee314693fae2c7aa1199c39b6 /tools/perf/scripts/python/bin/export-to-sqlite-record | |
| parent | KVM: x86: Mark TSS busy during LTR emulation _after_ all fault checks (diff) | |
| download | linux-2626206963ace9e8bf92b6eea5ff78dd674c555c.tar.gz linux-2626206963ace9e8bf92b6eea5ff78dd674c555c.zip | |
KVM: x86: Set error code to segment selector on LLDT/LTR non-canonical #GP
When injecting a #GP on LLDT/LTR due to a non-canonical LDT/TSS base, set
the error code to the selector. Intel SDM's says nothing about the #GP,
but AMD's APM explicitly states that both LLDT and LTR set the error code
to the selector, not zero.
Note, a non-canonical memory operand on LLDT/LTR does generate a #GP(0),
but the KVM code in question is specific to the base from the descriptor.
Fixes: e37a75a13cda ("KVM: x86: Emulator ignores LDTR/TR extended base on LLDT/LTR")
Cc: stable@vger.kernel.org
Signed-off-by: Sean Christopherson <seanjc@google.com>
Reviewed-by: Maxim Levitsky <mlevitsk@redhat.com>
Link: https://lore.kernel.org/r/20220711232750.1092012-3-seanjc@google.com
Signed-off-by: Sean Christopherson <seanjc@google.com>
Diffstat (limited to 'tools/perf/scripts/python/bin/export-to-sqlite-record')
0 files changed, 0 insertions, 0 deletions