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| author | Douglas Anderson <dianders@chromium.org> | 2019-12-18 14:35:26 -0800 |
|---|---|---|
| committer | Neil Armstrong <narmstrong@baylibre.com> | 2020-02-13 10:21:10 +0100 |
| commit | 457622d9f99b9b2b44375d7e5e95cde5f66910f9 (patch) | |
| tree | fd6b3acdab705487898b5dc0bb44e34300e0ed6a /tools/perf/scripts/python/bin/export-to-sqlite-record | |
| parent | drm/bridge: ti-sn65dsi86: Config number of DP lanes Mo' Betta (diff) | |
| download | linux-457622d9f99b9b2b44375d7e5e95cde5f66910f9.tar.gz linux-457622d9f99b9b2b44375d7e5e95cde5f66910f9.zip | |
drm/bridge: ti-sn65dsi86: Read num lanes from the DP sink
At least one panel hooked up to the bridge (AUO B116XAK01) only
supports 1 lane of DP. Let's read this information and stop
hardcoding 4 DP lanes.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191218143416.v3.5.Idbd0051d0de53f7e9d18a291ea33011c0854fcc6@changeid
Diffstat (limited to 'tools/perf/scripts/python/bin/export-to-sqlite-record')
0 files changed, 0 insertions, 0 deletions