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| author | Siddharth Vadapalli <s-vadapalli@ti.com> | 2024-05-02 14:39:59 +0530 |
|---|---|---|
| committer | Vignesh Raghavendra <vigneshr@ti.com> | 2024-06-12 21:31:26 +0530 |
| commit | 01bd39357b70ed41fb52b26c7e5b42de328fcdd4 (patch) | |
| tree | 4b775e2952665a65ae2d58c09ecfcc1740d0cc7a /tools/perf/scripts/python/bin/stackcollapse-record | |
| parent | arm64: dts: ti: k3-j784s4-evm: Add alias for MCU CPSW2G (diff) | |
| download | linux-01bd39357b70ed41fb52b26c7e5b42de328fcdd4.tar.gz linux-01bd39357b70ed41fb52b26c7e5b42de328fcdd4.zip | |
arm64: dts: ti: k3-j784s4-main: Add CPSW2G and CPSW9G nodes
J784S4 SoC has MAIN CPSW2G and CPSW9G instances of the CPSW
Ethernet Switch. CPSW2G has 1 external port and 1 host port
while CPSW9G has 8 external ports and 1 host port.
Add device-tree nodes for MAIN CPSW2G and CPSW9G and disable
them by default. MAIN CPSW2G will be enabled in the board file
while device-tree overlays will be used to enable CPSW9G.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: Chintan Vankar <c-vankar@ti.com>
Link: https://lore.kernel.org/r/20240502091002.3659435-3-c-vankar@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-record')
0 files changed, 0 insertions, 0 deletions