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| author | Tim Huang <tim.huang@amd.com> | 2022-10-24 11:05:59 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2022-11-29 11:03:37 -0500 |
| commit | 069a5af97ce3a1448a3566ce8b63b60e51e19958 (patch) | |
| tree | 7522ec3952dfbe13ebd0eca7c4df6af162a699cb /tools/perf/scripts/python/bin/stackcollapse-record | |
| parent | drm/amdgpu/soc21: add mode2 asic reset for SMU IP v13.0.11 (diff) | |
| download | linux-069a5af97ce3a1448a3566ce8b63b60e51e19958.tar.gz linux-069a5af97ce3a1448a3566ce8b63b60e51e19958.zip | |
drm/amdgpu/pm: use the specific mailbox registers only for SMU IP v13.0.4
The SMU IP v13.0.4 ppt interface is shared by IP v13.0.11, they use
the different mailbox register offset. So use the specific mailbox
registers offset for v13.0.4.
Signed-off-by: Tim Huang <tim.huang@amd.com>
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
Reviewed-by: Aaron Liu <aaron.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-record')
0 files changed, 0 insertions, 0 deletions