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| author | Aditya Swarup <aditya.swarup@intel.com> | 2020-03-18 18:59:41 -0700 |
|---|---|---|
| committer | Manasi Navare <manasi.d.navare@intel.com> | 2020-03-27 16:30:24 -0700 |
| commit | 106d4ffd6cb8f15f3b66c0f64c16dfeda4f395e2 (patch) | |
| tree | 5da0f9a6ea005df9b848222f41bc62e3d57ab458 /tools/perf/scripts/python/bin/stackcollapse-record | |
| parent | drm/i915/execlists: Workaround switching back to a completed context (diff) | |
| download | linux-106d4ffd6cb8f15f3b66c0f64c16dfeda4f395e2.tar.gz linux-106d4ffd6cb8f15f3b66c0f64c16dfeda4f395e2.zip | |
drm/i915/tgl: Add definitions for VRR registers and bits
Add definitions for registers grouped under Transcoder VRR function
with necessary bitfields.
Bspec: 49268
v2: Use REG_GENMASK, correct tabs/space indentation and move the
definitions near the transcoder section.(Jani)
v3: Remove unnecessary prefix from bit/mask definitions.(Manasi)
v4: Use 'trans' in macro for better readability.(Manasi)
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200319015941.28008-1-aditya.swarup@intel.com
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-record')
0 files changed, 0 insertions, 0 deletions