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| author | Martin Blumenstingl <martin.blumenstingl@googlemail.com> | 2020-04-17 20:41:27 +0200 |
|---|---|---|
| committer | Jerome Brunet <jbrunet@baylibre.com> | 2020-04-29 10:26:53 +0200 |
| commit | 16afd70af5b21b6d73a03b9c36f78b9cf004a0dd (patch) | |
| tree | a5f3d71ac5d846d3185682d5282def0833547a4a /tools/perf/scripts/python/bin/stackcollapse-record | |
| parent | clk: meson: meson8b: Fix the vclk_div{1, 2, 4, 6, 12}_en gate bits (diff) | |
| download | linux-16afd70af5b21b6d73a03b9c36f78b9cf004a0dd.tar.gz linux-16afd70af5b21b6d73a03b9c36f78b9cf004a0dd.zip | |
clk: meson: meson8b: Make the CCF use the glitch-free VPU mux
The "vpu_0" or "vpu_1" clock trees should not be updated while the
clock is running. Enforce this by setting CLK_SET_RATE_GATE on the
"vpu_0" and "vpu_1" gates. This makes the CCF switch to the "vpu_1"
tree when "vpu_0" is currently active and vice versa, which is exactly
what the vendor driver does when updating the frequency of the VPU
clock.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lore.kernel.org/r/20200417184127.1319871-5-martin.blumenstingl@googlemail.com
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-record')
0 files changed, 0 insertions, 0 deletions