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| author | David Zhang <dingchen.zhang@amd.com> | 2022-05-02 11:59:58 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2022-06-06 14:42:02 -0400 |
| commit | 32c453f18dccd93a27d6f026ca690167c8cc9639 (patch) | |
| tree | f6b2c507daf1e107be520518b8238c501ea25c4d /tools/perf/scripts/python/bin/stackcollapse-record | |
| parent | 65657d98754c581ad66b56680d3c9ed679890071 (diff) | |
| download | linux-32c453f18dccd93a27d6f026ca690167c8cc9639.tar.gz linux-32c453f18dccd93a27d6f026ca690167c8cc9639.zip | |
drm/amd/display: add vline time in micro sec to PSR context
[why]
The current PSR SU programming margin is fixed base on FHD 60HZ
panel. If the resolution and refresh rate become higher, the time
of current margin might not cover the programming SU time.
[how]
Notice that the programming SU time is the same among different
panels.
Instead of fixing the margin with target line number, change the
margin unit to micro second which indicate the time needed for
programming SU. Then FW set the margin line number base on the
line time and margin time.
Signed-off-by: David Zhang <dingchen.zhang@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-record')
0 files changed, 0 insertions, 0 deletions