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| author | Xiang Chen <chenxiang66@hisilicon.com> | 2017-06-14 23:33:22 +0800 |
|---|---|---|
| committer | Martin K. Petersen <martin.petersen@oracle.com> | 2017-06-19 21:31:26 -0400 |
| commit | 3975f6054e31c55c7e73faa342780e2af2f30872 (patch) | |
| tree | 72d7dd3f0c757a3c87ca96c934031a061c411641 /tools/perf/scripts/python/bin/stackcollapse-record | |
| parent | scsi: hisi_sas: add v3 hw init (diff) | |
| download | linux-3975f6054e31c55c7e73faa342780e2af2f30872.tar.gz linux-3975f6054e31c55c7e73faa342780e2af2f30872.zip | |
scsi: hisi_sas: add v3 hw PHY init
Add code to configure PHYs for v3 hw.
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-record')
0 files changed, 0 insertions, 0 deletions