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authorGuilherme G. Piccoli <gpiccoli@igalia.com>2022-10-06 19:42:07 -0300
committerKees Cook <keescook@chromium.org>2022-10-17 13:14:10 -0700
commit6a14f1982e6b476c84938c9ca011d258a6bba24d (patch)
tree6a724d6da0d3ec862b10314887a37fa3692169e5 /tools/perf/scripts/python/bin/stackcollapse-record
parentpstore: Expose kmsg_bytes as a module parameter (diff)
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pstore: Inform unregistered backend names as well
Currently we only show the registered ones in the kernel log; users that change backend for some reason require first to unregister the current one, so let's confirm this operation with a message in the log. Signed-off-by: Guilherme G. Piccoli <gpiccoli@igalia.com> Signed-off-by: Kees Cook <keescook@chromium.org> Link: https://lore.kernel.org/r/20221006224212.569555-4-gpiccoli@igalia.com
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-record')
0 files changed, 0 insertions, 0 deletions
commit/arch/sh/kernel/signal_64.c?id=b613881ead41c8fc2e1413aeb6ef8f021f00c1e7&follow=1'>sh: flush_cache_sigtramp() takes 1 arg only.Paul Mundt1-1/+1 2008-01-28sh: Move vsyscall_init() defs up one level.Paul Mundt2-6/+6 2008-01-28sh: Nopped out p3_cache_init() on SH-5 also.Paul Mundt1-0/+1 2008-01-28sh: Fix up VMALLOC_START for SH-5.Paul Mundt1-0/+4 2008-01-28sh: Move over the SH-5 head.S and tlb.h.Paul Mundt6-44/+24 2008-01-28sh: Have SH-5 provide an {en,dis}able_fpu() impl.Paul Mundt3-10/+21 2008-01-28sh: Disable initial cache flush on SH-5.Paul Mundt1-14/+18 2008-01-28sh: Don't reference UBC code in CPU init on sh64.Paul Mundt1-1/+6 2008-01-28sh: imask IRQ depends on sh32.Paul Mundt1-1/+2 2008-01-28sh: Move in the SH-5 traps.c impl.Paul Mundt4-3/+2