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authorAmelie Delaunay <amelie.delaunay@foss.st.com>2021-02-08 12:46:59 +0100
committerVinod Koul <vkoul@kernel.org>2021-03-15 15:25:29 +0530
commit7bc057dd65ab02995f21fa3b0f9d97261cd5aa2a (patch)
tree6471981d71089dd55b1d97d929630753e4238a5d /tools/perf/scripts/python/bin/stackcollapse-record
parentdt-bindings: phy: phy-stm32-usbphyc: add #clock-cells property (diff)
downloadlinux-7bc057dd65ab02995f21fa3b0f9d97261cd5aa2a.tar.gz
linux-7bc057dd65ab02995f21fa3b0f9d97261cd5aa2a.zip
phy: stm32: register usbphyc as clock provider of ck_usbo_48m clock
ck_usbo_48m is generated by usbphyc PLL and used by OTG controller for Full-Speed use cases with dedicated Full-Speed transceiver. ck_usbo_48m is available as soon as the PLL is enabled. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20210208114659.15269-3-amelie.delaunay@foss.st.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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