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| author | José Roberto de Souza <jose.souza@intel.com> | 2018-12-03 16:33:58 -0800 |
|---|---|---|
| committer | José Roberto de Souza <jose.souza@intel.com> | 2018-12-04 12:12:31 -0800 |
| commit | 98751b8cd608a38f810e190c58c94906923ff668 (patch) | |
| tree | af691895ee7c0fac1e2df30234d4cc959cf4e221 /tools/perf/scripts/python/bin/stackcollapse-record | |
| parent | drm/i915/psr: Set PSR CRC verification bit in sink inside PSR1 block (diff) | |
| download | linux-98751b8cd608a38f810e190c58c94906923ff668.tar.gz linux-98751b8cd608a38f810e190c58c94906923ff668.zip | |
drm/i915/psr: Enable sink to trigger a interruption on PSR2 CRC mismatch
eDP spec states 2 different bits to enable sink to trigger a
interruption when there is a CRC mismatch.
DP_PSR_CRC_VERIFICATION is for PSR only and
DP_PSR_IRQ_HPD_WITH_CRC_ERRORS is for PSR2 only.
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181204003403.23361-4-jose.souza@intel.com
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-record')
0 files changed, 0 insertions, 0 deletions