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authorKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>2024-07-03 11:42:40 +0200
committerBjorn Andersson <andersson@kernel.org>2024-07-06 12:56:50 -0500
commitb066a2c430f3f8d0aedba44991e0a69e21b512d3 (patch)
tree3668cae7dc8a03589706dee57887f8fbbc04e2fc /tools/perf/scripts/python/bin/stackcollapse-record
parentsoc: qcom: pdr: simplify with cleanup.h (diff)
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soc: qcom: wcnss: simplify with cleanup.h
Allocate the memory with scoped/cleanup.h to reduce error handling (less error paths) and make the code a bit simpler. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240703-thermal-const-v1-5-6e59e139c65d@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-record')
0 files changed, 0 insertions, 0 deletions
e='2008-01-28 13:18:44 +0900'>2008-01-28sh: flush_cache_sigtramp() takes 1 arg only.Paul Mundt1-1/+1 2008-01-28sh: Move vsyscall_init() defs up one level.Paul Mundt2-6/+6 2008-01-28sh: Nopped out p3_cache_init() on SH-5 also.Paul Mundt1-0/+1 2008-01-28sh: Fix up VMALLOC_START for SH-5.Paul Mundt1-0/+4 2008-01-28sh: Move over the SH-5 head.S and tlb.h.Paul Mundt6-44/+24 2008-01-28sh: Have SH-5 provide an {en,dis}able_fpu() impl.Paul Mundt3-10/+21 2008-01-28sh: Disable initial cache flush on SH-5.Paul Mundt1-14/+18 2008-01-28sh: Don't reference UBC code in CPU init on sh64.Paul Mundt1-1/+6 2008-01-28sh: imask IRQ depends on sh32.Paul Mundt1-1/+2 2008-01-28sh: Move in the SH-5 traps.c impl.Paul Mundt4-3/+2