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| author | Madhumitha Tolakanahalli Pradeep <madhumitha.tolakanahalli.pradeep@intel.com> | 2023-04-21 20:25:34 +0200 |
|---|---|---|
| committer | Andi Shyti <andi.shyti@linux.intel.com> | 2023-04-23 02:11:21 +0200 |
| commit | b76c0deef6273609c02ed5053209f6397cd1b0fb (patch) | |
| tree | 809d4600b1e64838d3e484898fbefaa0233c9b2d /tools/perf/scripts/python/bin/stackcollapse-record | |
| parent | drm/i915/mtl: Set has_llc=0 (diff) | |
| download | linux-b76c0deef6273609c02ed5053209f6397cd1b0fb.tar.gz linux-b76c0deef6273609c02ed5053209f6397cd1b0fb.zip | |
drm/i915/mtl: Define MOCS and PAT tables for MTL
On MTL, GT can no longer allocate on LLC - only the CPU can.
This, along with programming new register bits that MTL
requires calls for a MOCS/PAT table update.
Also the PAT index registers are multicasted for primary GT,
and there is an address jump from index 7 to 8. This patch
makes sure that these registers are programmed in the proper
way.
BSpec: 44509, 45101, 44235
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Madhumitha Tolakanahalli Pradeep <madhumitha.tolakanahalli.pradeep@intel.com>
Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
Signed-off-by: Fei Yang <fei.yang@intel.com>
Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230421182535.292670-2-andi.shyti@linux.intel.com
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-record')
0 files changed, 0 insertions, 0 deletions