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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2025-09-23 20:19:29 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2025-10-11 02:50:01 +0300 |
| commit | bcc492d712f53946c4b434e2fad5650637af0c68 (patch) | |
| tree | d1950e30f1e33a1b83f4082b02d25847b05c8f0c /tools/perf/scripts/python/bin/stackcollapse-record | |
| parent | 9112ce99c1d7ef9ba51c930913e791fcac824f62 (diff) | |
| download | linux-bcc492d712f53946c4b434e2fad5650637af0c68.tar.gz linux-bcc492d712f53946c4b434e2fad5650637af0c68.zip | |
drm/i915/cdclk: Introduce intel_cdclk_modeset_checks()
I plan to better decouple the cdclk computation from actual
modesets. To that end make the cdclk code self sufficient in
being able to determine if a full cdclk calculation/update is
needed or not due to some not strictly cdclk related reason.
Currently we have three such things that depend active_pipes:
- cdclk_state->actual
- glk audio w/a
- dg2 power well stuff
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250923171943.7319-8-ville.syrjala@linux.intel.com
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-record')
0 files changed, 0 insertions, 0 deletions