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| author | George Shen <George.Shen@amd.com> | 2021-11-17 20:49:50 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2021-12-01 16:06:25 -0500 |
| commit | c11099b0d1aa3e48e9578b440886d8b29779e8ba (patch) | |
| tree | 65e71bec09dccfea89550cd8e197763cd3d447f3 /tools/perf/scripts/python/bin/stackcollapse-record | |
| parent | drm/amd/display: PSR panel capability debugfs (diff) | |
| download | linux-c11099b0d1aa3e48e9578b440886d8b29779e8ba.tar.gz linux-c11099b0d1aa3e48e9578b440886d8b29779e8ba.zip | |
drm/amd/display: Add vendor specific LTTPR workarounds for DCN31
[Why]
Certain LTTPR require special workarounds in order to comply
with DP specifications.
[How]
Implement vendor specific sequences via DPCD writes to
vendor-specific LTTPR registers.
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: George Shen <George.Shen@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-record')
0 files changed, 0 insertions, 0 deletions