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| author | André Draszik <andre.draszik@linaro.org> | 2024-05-07 15:14:48 +0100 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2024-06-12 16:47:29 +0530 |
| commit | d14c14618e851eb25d55807810c2c1791a637712 (patch) | |
| tree | c68d098392fee20803ecc730f392414b5f635737 /tools/perf/scripts/python/bin/stackcollapse-record | |
| parent | phy: exynos5-usbdrd: fix definition of EXYNOS5_FSEL_26MHZ (diff) | |
| download | linux-d14c14618e851eb25d55807810c2c1791a637712.tar.gz linux-d14c14618e851eb25d55807810c2c1791a637712.zip | |
phy: exynos5-usbdrd: set ref clk freq in exynos850_usbdrd_utmi_init()
While commit 255ec3879dd4 ("phy: exynos5-usbdrd: Add 26MHz ref clk
support") correctly states that CLKRSTCTRL[7:5] doesn't need to be set
on modern Exynos platforms, SSPPLLCTL[2:0] should be programmed with
the frequency of the reference clock for the USB2.0 phy instead.
I stumbled across this while adding support for the Google Tensor
gs101, but this should apply to E850 just the same.
Do so.
Signed-off-by: André Draszik <andre.draszik@linaro.org>
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://lore.kernel.org/r/20240507-samsung-usb-phy-fixes-v1-5-4ccba5afa7cc@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-record')
0 files changed, 0 insertions, 0 deletions