diff options
| author | Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2025-05-13 16:46:34 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2025-06-10 10:20:45 +0200 |
| commit | e018f9f8973760faacbdf9bf678fdb46c1f591c8 (patch) | |
| tree | b97651937da043e53c7d17dada4d1eaafde05dff /tools/perf/scripts/python/bin/stackcollapse-record | |
| parent | clk: renesas: r9a09g056: Add clock and reset entries for RIIC controllers (diff) | |
| download | linux-e018f9f8973760faacbdf9bf678fdb46c1f591c8.tar.gz linux-e018f9f8973760faacbdf9bf678fdb46c1f591c8.zip | |
clk: renesas: r9a09g056: Add clock and reset entries for WDT controllers
Add module clock and reset definitions for WDT0-3, which are available
on the RZ/V2N (R9A09G056) SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250513154635.273664-5-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-record')
0 files changed, 0 insertions, 0 deletions