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| author | Gevorg Sahakyan <Gevorg.Sahakyan@synopsys.com> | 2018-07-26 18:00:13 +0400 |
|---|---|---|
| committer | Felipe Balbi <felipe.balbi@linux.intel.com> | 2018-07-30 10:39:16 +0300 |
| commit | f25c42b8d604fbca6d8d3eff2365a73bbef076d3 (patch) | |
| tree | 7400ccbb88912e79db006043fb0103b7f1359bb3 /tools/perf/scripts/python/bin/stackcollapse-record | |
| parent | usb: dwc3: pci: Intel Merrifield can be host (diff) | |
| download | linux-f25c42b8d604fbca6d8d3eff2365a73bbef076d3.tar.gz linux-f25c42b8d604fbca6d8d3eff2365a73bbef076d3.zip | |
usb: dwc2: Modify dwc2_readl/writel functions prototype
Added hsotg argument to dwc2_readl/writel function prototype,
and also instead of address pass offset of register.
hsotg will contain flag field for endianness.
Also customized dwc2_set_bit and dwc2_clear_bit function for
dwc2_readl/writel functions.
Signed-off-by: Gevorg Sahakyan <sahakyan@synopsys.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-record')
0 files changed, 0 insertions, 0 deletions