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authorSean Christopherson <seanjc@google.com>2021-09-20 17:02:56 -0700
committerPaolo Bonzini <pbonzini@redhat.com>2021-09-30 04:27:05 -0400
commitff8828c84f9376a8c3040da16a88e2c39aa3a527 (patch)
treef623451970af0cc4a2c6ee16e359431777fbfbbc /tools/perf/scripts/python/bin/stackcollapse-record
parentKVM: x86: Simplify retrieving the page offset when loading PDTPRs (diff)
downloadlinux-ff8828c84f9376a8c3040da16a88e2c39aa3a527.tar.gz
linux-ff8828c84f9376a8c3040da16a88e2c39aa3a527.zip
KVM: x86: Do not mark all registers as avail/dirty during RESET/INIT
Do not blindly mark all registers as available+dirty at RESET/INIT, and instead rely on writes to registers to go through the proper mutators or to explicitly mark registers as dirty. INIT in particular does not blindly overwrite all registers, e.g. select bits in CR0 are preserved across INIT, thus marking registers available+dirty without first reading the register from hardware is incorrect. In practice this is a benign bug as KVM doesn't let the guest control CR0 bits that are preserved across INIT, and all other true registers are explicitly written during the RESET/INIT flows. The PDPTRs and EX_INFO "registers" are not explicitly written, but accessing those values during RESET/INIT is nonsensical and would be a KVM bug regardless of register caching. Fixes: 66f7b72e1171 ("KVM: x86: Make register state after reset conform to specification") [sean: !!! NOT FOR STABLE !!!] Signed-off-by: Sean Christopherson <seanjc@google.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210921000303.400537-4-seanjc@google.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-record')
0 files changed, 0 insertions, 0 deletions
59:15 +0200'>2008-09-19AMD IOMMU: add MSI interrupt supportJoerg Roedel5-1/+120 2008-09-19AMD IOMMU: save pci_dev instead of devidJoerg Roedel2-11/+19 2008-09-19AMD IOMMU: save pci segment from ACPI tablesJoerg Roedel2-0/+4 2008-09-19AMD IOMMU: add event buffer allocationJoerg Roedel2-0/+38 2008-09-19AMD IOMMU: align alloc_coherent addresses properlyJoerg Roedel1-8/+14 2008-09-19AMD IOMMU: add branch hints to completion wait checksJoerg Roedel1-6/+6 2008-09-19AMD IOMMU: implement lazy IO/TLB flushingJoerg Roedel3-5/+31 2008-09-19x86: move GART TLB flushing options to generic codeJoerg Roedel5-15/+18 2008-09-19AMD IOMMU: move TLB flushing to the map/unmap helper functionsJoerg Roedel1-14/+5 2008-09-19AMD IOMMU: check for invalid device pointersJoerg Roedel1-8/+35 2008-09-19convert swiotlb to use dma_get_maskFUJITA Tomonori2-6/+2 2008-09-14x86: gart alloc_coherent does virtual mapppings only when necessaryFUJITA Tomonori1-1/+9 2008-09-14x86: avoid unnecessary low zone allocation in Calgary's alloc_coherentFUJITA Tomonori1-0/+2 2008-09-14x86: make GART to respect device's dma_mask about virtual mappingsFUJITA Tomonori1-11/+28 2008-09-14iommu: add dma_get_mask helper functionFUJITA Tomonori1-0/+7 2008-09-14iommu: add iommu_device_max_index IOMMU helper functionFUJITA Tomonori1-0/+10 2008-09-13memstick: fix MSProHG 8-bit interface mode supportAlex Dubov4-73/+106 2008-09-13rescan_partitions(): make device capacity errors non-fatalAndrew Morton1-2/+2 2008-09-13spi_s3c24xx: fix section warningBen Dooks1-3/+3 2008-09-13atmel_lcdfb: disable LCD and DMA engines when suspendingHaavard Skinnemoen1-35/+49 2008-09-13ia64: fix panic during `modprobe -r xpc'Robin Holt1-0/+3 2008-09-13MAINTAINERS: fix USB VIDEO CLASS mail list addressMing Lei1-1/+1