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| author | Matt Roper <matthew.d.roper@intel.com> | 2020-02-06 16:14:17 -0800 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2020-02-10 09:51:44 -0800 |
| commit | 0fde0b1daac97ae6e51a85e44cd461a8366d8997 (patch) | |
| tree | 208f59264f0c29fc1e32b3d4e8d1cd0fb60c57e8 /tools/perf/scripts/python/bin/stackcollapse-report | |
| parent | drm/i915/ehl: Update port clock voltage level requirements (diff) | |
| download | linux-0fde0b1daac97ae6e51a85e44cd461a8366d8997.tar.gz linux-0fde0b1daac97ae6e51a85e44cd461a8366d8997.zip | |
drm/i915/tgl: Update cdclk voltage level settings
A recent bspec update added an extra voltage level that we didn't have
on ICL and new criteria for selecting the level.
Bspec: 49208
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200207001417.1229251-2-matthew.d.roper@intel.com
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-report')
0 files changed, 0 insertions, 0 deletions