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| author | Dinh Nguyen <dinguyen@kernel.org> | 2022-01-25 10:18:20 -0600 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2022-02-11 11:15:22 +0100 |
| commit | 3d8d3504d23351bcbab7be08f82c5dfabc3c9e0a (patch) | |
| tree | cfbe55ec68d95019f5a02608002ba9026831740c /tools/perf/scripts/python/bin/stackcollapse-report | |
| parent | dt-bindings: usb: dwc2: add compatible "intel,socfpga-agilex-hsotg" (diff) | |
| download | linux-3d8d3504d23351bcbab7be08f82c5dfabc3c9e0a.tar.gz linux-3d8d3504d23351bcbab7be08f82c5dfabc3c9e0a.zip | |
usb: dwc2: Add platform specific data for Intel's Agilex
The DWC2 IP on the Agilex platform does not support clock-gating.
Acked-by: Minas Harutyunyan <Minas.Harutyunyan@synopsys.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Link: https://lore.kernel.org/r/20220125161821.1951906-2-dinguyen@kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-report')
0 files changed, 0 insertions, 0 deletions