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| author | Hawking Zhang <Hawking.Zhang@amd.com> | 2020-11-25 15:25:51 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2020-12-23 15:05:07 -0500 |
| commit | 78bd101cdfe20913ef76759b344adc5223dff006 (patch) | |
| tree | 4b321eaf7a212d07e4964a39a0fdd7e695b9bd66 /tools/perf/scripts/python/bin/stackcollapse-report | |
| parent | drm/amdgpu: use cached ih rb control reg offsets for navi10 (diff) | |
| download | linux-78bd101cdfe20913ef76759b344adc5223dff006.tar.gz linux-78bd101cdfe20913ef76759b344adc5223dff006.zip | |
drm/amdgpu: add a helper function to decode iv
since from soc15, all the chips share the same
iv format. create a common helper to decode iv
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Dennis Li <Dennis.Li@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-report')
0 files changed, 0 insertions, 0 deletions