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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2024-03-08 09:24:00 +0200 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2024-03-20 15:26:42 +0200 |
| commit | 8353939042e8f8de8c0f98937f42c04eba7c06cd (patch) | |
| tree | 02b01e0df77685de27f4780b89d67b76b6c49066 /tools/perf/scripts/python/bin/stackcollapse-report | |
| parent | drm/i915/scaler: Update Pipe src size check in skl_update_scaler (diff) | |
| download | linux-8353939042e8f8de8c0f98937f42c04eba7c06cd.tar.gz linux-8353939042e8f8de8c0f98937f42c04eba7c06cd.zip | |
drm/i915: Rename ICL_PORT_TX_DW6 bits
Our definitions for bit 7 and bit 0 of ICL_PORT_TX_DW6 are
swapped. Functionally it doesn't matter as we always set both
bits, but let's rename the bits to match bspec 100%.
And while at it, add the definition for bits 1-6 as well, just
to have it all fully documented.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240308072400.28918-1-ville.syrjala@linux.intel.com
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-report')
0 files changed, 0 insertions, 0 deletions