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| author | Xiaojie Yuan <xiaojie.yuan@amd.com> | 2019-08-21 21:00:29 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-08-22 17:25:01 -0500 |
| commit | 9e48495017342c5d445b25eedd86d6fd884a6496 (patch) | |
| tree | ff150afc5849621f995f4e18aebfc24693495c4d /tools/perf/scripts/python/bin/stackcollapse-report | |
| parent | drm/amd/display: Enable SST DSC in DM (diff) | |
| download | linux-9e48495017342c5d445b25eedd86d6fd884a6496.tar.gz linux-9e48495017342c5d445b25eedd86d6fd884a6496.zip | |
drm/amdgpu/sdma5: fix number of sdma5 trap irq types for navi1x
v2: set num_types based on num_instances
navi1x has 2 sdma engines but commit
"e7b58d03b678 drm/amdgpu: reorganize sdma v4 code to support more instances"
changes the max number of sdma irq types (AMDGPU_SDMA_IRQ_LAST) from 2 to 8
which causes amdgpu_irq_gpu_reset_resume_helper() to recover irq of sdma
engines with following logic:
(enable irq for sdma0) * 1 time
(enable irq for sdma1) * 1 time
(disable irq for sdma1) * 6 times
as a result, after gpu reset, interrupt for sdma1 is lost.
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-report')
0 files changed, 0 insertions, 0 deletions